| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.c | 28 TEST2("drotr $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1); in main()
29 TEST2("drotr $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3); in main()
30 TEST2("drotr $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1); in main()
31 TEST2("drotr $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1); in main()
41 TEST2("drotr32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1); in main()
42 TEST2("drotr32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3); in main()
43 TEST2("drotr32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1); in main()
44 TEST2("drotr32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1); in main()
52 TEST1("drotrv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
61 TEST2("dsll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1); in main()
[all …]
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| D | arithmetic_instruction.c | 93 TEST2("daddi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); in main()
94 TEST2("daddi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); in main()
95 TEST2("daddi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); in main()
96 TEST2("daddi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); in main()
106 TEST2("daddiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); in main()
107 TEST2("daddiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); in main()
108 TEST2("daddiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); in main()
109 TEST2("daddiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); in main()
117 TEST1("daddu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
124 TEST3("dclo $v0, $v1", reg_val2[i], v0, v1); in main()
[all …]
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| D | logical_instructions.c | 23 TEST1("and $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
34 TEST2("andi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); in main()
35 TEST2("andi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); in main()
36 TEST2("andi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); in main()
37 TEST2("andi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); in main()
56 TEST1("nor $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
64 TEST1("or $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
74 TEST2("ori $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); in main()
75 TEST2("ori $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); in main()
76 TEST2("ori $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); in main()
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| D | load_store.c | 18 TEST1("lb", i, reg_val2); in main()
25 TEST1("lbu", i, reg_val2); in main()
32 TEST1("ld", i, reg_val2); in main()
39 TEST1("ldl", i, reg_val2); in main()
46 TEST1("ldr", i, reg_val2); in main()
53 TEST1("lh", i, reg_val2); in main()
60 TEST1("lhu", i, reg_val2); in main()
67 TEST1("lw", i, reg_val2); in main()
74 TEST1("lwl", i, reg_val2); in main()
81 TEST1("lwr", i, reg_val2); in main()
[all …]
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| D | const.h | 70 unsigned long long reg_val2[N]; variable
76 reg_val2[0]= c & 0xffffffffUL; in init_reg_val2()
78 reg_val2[i] = (1812433253UL * (reg_val2[i - 1] ^ in init_reg_val2()
79 (reg_val2[i - 1] >> 30)) + i); in init_reg_val2()
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| D | fpu_load_store.c | 19 TEST3("ldc1", i, reg_val2); in main()
26 TEST5("ldxc1", i, reg_val2); in main()
33 TEST3w("lwc1", i, reg_val2); in main()
40 TEST5w("lwxc1", i, reg_val2); in main()
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| D | macro_load_store.h | 40 : "r" (reg_val2) , "r" (reg_val_zero), "r" (offset) \
154 : "r" (reg_val2) , "r" (reg_val_zero), "r" (offset) \
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| D | move_instructions.c | 205 TEST1(reg_val2[i]); in main()
206 TEST2(reg_val2[i]); in main()
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