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Searched refs:regid (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_shader.c78 int32_t regid = (v->inputs[i].regid + 3) >> 2; in fixup_regfootprint() local
79 v->info.max_reg = MAX2(v->info.max_reg, regid); in fixup_regfootprint()
83 int32_t regid = (v->outputs[i].regid + 3) >> 2; in fixup_regfootprint() local
84 v->info.max_reg = MAX2(v->info.max_reg, regid); in fixup_regfootprint()
320 if (r != regid(63,0)) in dump_reg()
327 uint32_t regid; in dump_output() local
328 regid = ir3_find_output_regid(so, slot); in dump_output()
329 dump_reg(name, regid); in dump_output()
338 uint8_t regid; in ir3_shader_disasm() local
347 regid = reg->num; in ir3_shader_disasm()
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Dir3_shader.h161 uint8_t regid; member
171 uint8_t regid; member
342 uint8_t regid; member
349 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc) in ir3_link_add() argument
355 l->var[i].regid = regid; in ir3_link_add()
379 ir3_link_add(l, vs->outputs[k].regid, in ir3_link_shaders()
390 return so->outputs[j].regid; in ir3_find_output_regid()
391 return regid(63, 0); in ir3_find_output_regid()
400 return so->inputs[j].regid; in ir3_find_sysval_regid()
401 return regid(63, 0); in ir3_find_sysval_regid()
Dir3_compiler_nir.c353 instr->regs[0]->num = regid(REG_A0, 0); in create_addr()
395 cond->regs[0]->num = regid(REG_P0, 0); in get_predicate()
601 unsigned r = regid(n + dp / 4, dp % 4); in create_driver_param()
999 unsigned ubo = regid(ctx->so->constbase.ubo, 0); in emit_intrinsic_load_ubo()
1143 unsigned r = regid(so->inputs_count, 0); in add_sysval_input()
1149 so->inputs[n].regid = r; in add_sysval_input()
1306 cond->regs[0]->num = regid(REG_P0, 0); in emit_intrinsic()
1930 cond->regs[0]->num = regid(REG_P0, 0); in emit_stream_out()
1952 base = create_uniform(ctx, regid(v->constbase.tfbo, i)); in emit_stream_out()
1968 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)]; in emit_stream_out()
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Dir3_legalize.c138 if (last_rel && (reg->num == regid(REG_A0, 0))) { in legalize_block()
220 ir3_reg_create(baryf, regid(63, 0), 0); in legalize_block()
222 ir3_reg_create(baryf, regid(0, 0), 0); in legalize_block()
Dir3.h513 static inline uint32_t regid(int num, int comp) in regid() function
552 if (dst->num == regid(REG_P0, 0)) in is_same_type_mov()
554 if (dst->num == regid(REG_A0, 0)) in is_same_type_mov()
Dir3_ra.c311 if ((reg->num == regid(REG_A0, 0)) || in is_temp()
312 (reg->num == regid(REG_P0, 0))) in is_temp()
Dir3_cp.c540 (instr->regs[0]->num == regid(REG_P0, 0)) && in instr_cp()
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_emit.c59 uint32_t regid, uint32_t offset, uint32_t sizedwords, in fd4_emit_const() argument
65 debug_assert((regid % 4) == 0); in fd4_emit_const()
77 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) | in fd4_emit_const()
97 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets) in fd4_emit_const_bo() argument
102 debug_assert((regid % 4) == 0); in fd4_emit_const_bo()
105 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) | in fd4_emit_const_bo()
374 unsigned vertex_regid = regid(63, 0); in fd4_emit_vertex_bufs()
375 unsigned instance_regid = regid(63, 0); in fd4_emit_vertex_bufs()
376 unsigned vtxcnt_regid = regid(63, 0); in fd4_emit_vertex_bufs()
388 vertex_regid = vp->inputs[i].regid; in fd4_emit_vertex_bufs()
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Dfd4_program.c238 if (pos_regid == regid(63, 0)) { in fd4_program_emit()
243 pos_regid = regid(0, 0); in fd4_program_emit()
263 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0); in fd4_program_emit()
264 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0); in fd4_program_emit()
265 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0); in fd4_program_emit()
353 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd4_program_emit()
357 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd4_program_emit()
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_emit.c59 uint32_t regid, uint32_t offset, uint32_t sizedwords, in fd3_emit_const() argument
65 debug_assert((regid % 4) == 0); in fd3_emit_const()
77 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) | in fd3_emit_const()
97 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets) in fd3_emit_const_bo() argument
102 debug_assert((regid % 4) == 0); in fd3_emit_const_bo()
105 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) | in fd3_emit_const_bo()
367 unsigned vertex_regid = regid(63, 0); in fd3_emit_vertex_bufs()
368 unsigned instance_regid = regid(63, 0); in fd3_emit_vertex_bufs()
369 unsigned vtxcnt_regid = regid(63, 0); in fd3_emit_vertex_bufs()
381 vertex_regid = vp->inputs[i].regid; in fd3_emit_vertex_bufs()
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Dfd3_program.c242 COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) | in fd3_program_emit()
243 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(regid(0,2)))); in fd3_program_emit()
286 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd3_program_emit()
290 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); in fd3_program_emit()
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_program.c162 if (l->var[idx].regid == v->outputs[k].regid) in link_stream_out()
169 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc); in link_stream_out()
206 if (l->var[idx].regid == v->outputs[k].regid) in emit_stream_out()
368 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0); in fd5_program_emit()
369 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0); in fd5_program_emit()
370 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0); in fd5_program_emit()
371 vcoord_regid = (s[FS].v->total_in > 0) ? s[FS].v->pos_regid : regid(63,0); in fd5_program_emit()
476 if (pos_regid != regid(63,0)) in fd5_program_emit()
479 if (psize_regid != regid(63,0)) { in fd5_program_emit()
500 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); in fd5_program_emit()
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Dfd5_emit.c57 uint32_t regid, uint32_t offset, uint32_t sizedwords, in fd5_emit_const() argument
63 debug_assert((regid % 4) == 0); in fd5_emit_const()
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) | in fd5_emit_const()
96 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets) in fd5_emit_const_bo() argument
101 debug_assert((regid % 4) == 0); in fd5_emit_const_bo()
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) | in fd5_emit_const_bo()
389 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid)); in fd5_emit_vertex_bufs()
554 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0))); in fd5_emit_state()
/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_context.h273 uint32_t regid, uint32_t offset, uint32_t sizedwords,
277 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets);
/external/autotest/client/site_tests/kernel_CheckArmErrata/
Dkernel_CheckArmErrata.py134 _, _, regid, val = line.split(":")
135 regid_to_val[regid.strip()] = int(val, 0)
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_valtable.cpp328 value* sb_value_pool::create(value_kind k, sel_chan regid, in create() argument
331 value *v = new (np) value(size(), k, regid, ver); in create()
Dsb_shader.cpp245 value* shader::create_value(value_kind k, sel_chan regid, unsigned ver) { in create_value() argument
246 value *v = val_pool.create(k, regid, ver); in create_value()
Dsb_shader.h409 value* create_value(value_kind k, sel_chan regid, unsigned ver);
Dsb_ir.h292 value* create(value_kind k, sel_chan regid, unsigned ver);