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Searched refs:res4 (Results 1 – 25 of 57) sorted by relevance

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/external/llvm/test/Bitcode/
DbinaryIntInstructions.3.2.ll19 ; CHECK-NEXT: %res4 = add i32 %x4, %x4
20 %res4 = add i32 %x4, %x4
48 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
49 %res4 = add nuw nsw <8 x i8> %x4, %x4
68 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
69 %res4 = add nuw nsw <8 x i16> %x4, %x4
88 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4
89 %res4 = add nuw nsw <8 x i32> %x4, %x4
108 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4
109 %res4 = add nuw nsw <8 x i64> %x4, %x4
[all …]
DbinaryFloatInstructions.3.2.ll19 ; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
20 %res4 = fadd fp128 %x4, %x4
42 ; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
43 %res4 = fadd <8 x float> %x4, %x4
62 ; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
63 %res4 = fadd <8 x double> %x4, %x4
82 ; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4
83 %res4 = fadd <8 x half> %x4, %x4
DconstantsTest.3.2.ll33 ; CHECK-NEXT: %res4 = fadd float 0.000000e+00, 0.000000e+00
34 %res4 = fadd float 0.0, 0.0
54 ; CHECK-NEXT: %res4 = add <2 x i32> %x, zeroinitializer
55 %res4 = add <2 x i32> %x, zeroinitializer
DaggregateInstructions.3.2.ll19 ; CHECK-NEXT: %res4 = extractvalue { { i32, float } } %x3, 0, 1
20 %res4 = extractvalue {{i32, float}} %x3, 0, 1
DbitwiseInstructions.3.2.ll19 ; CHECK: %res4 = shl nuw nsw i8 %x1, %x1
20 %res4 = shl nuw nsw i8 %x1, %x1
/external/llvm/test/CodeGen/X86/
Davx512ifmavl-intrinsics.ll26 %res4 = add <2 x i64> %res, %res1
28 %res6 = add <2 x i64> %res5, %res4
54 %res4 = add <4 x i64> %res, %res1
56 %res6 = add <4 x i64> %res5, %res4
82 %res4 = add <2 x i64> %res, %res1
84 %res6 = add <2 x i64> %res5, %res4
110 %res4 = add <4 x i64> %res, %res1
112 %res6 = add <4 x i64> %res5, %res4
138 %res4 = add <2 x i64> %res, %res1
140 %res6 = add <2 x i64> %res5, %res4
[all …]
Davx512vbmi-intrinsics.ll19 %res4 = add <64 x i8> %res3, %res2
20 ret <64 x i8> %res4
36 %res4 = add <64 x i8> %res3, %res2
37 ret <64 x i8> %res4
58 %res4 = add <64 x i8> %res3, %res2
59 ret <64 x i8> %res4
80 %res4 = add <64 x i8> %res3, %res2
81 ret <64 x i8> %res4
Davx512vbmivl-intrinsics.ll19 %res4 = add <16 x i8> %res3, %res2
20 ret <16 x i8> %res4
39 %res4 = add <32 x i8> %res3, %res2
40 ret <32 x i8> %res4
59 %res4 = add <16 x i8> %res3, %res2
60 ret <16 x i8> %res4
79 %res4 = add <32 x i8> %res3, %res2
80 ret <32 x i8> %res4
101 %res4 = add <16 x i8> %res3, %res2
102 ret <16 x i8> %res4
[all …]
Davx512ifma-intrinsics.ll23 %res4 = add <8 x i64> %res, %res1
25 %res6 = add <8 x i64> %res5, %res4
49 %res4 = add <8 x i64> %res, %res1
51 %res6 = add <8 x i64> %res5, %res4
75 %res4 = add <8 x i64> %res, %res1
77 %res6 = add <8 x i64> %res5, %res4
101 %res4 = add <8 x i64> %res, %res1
103 %res6 = add <8 x i64> %res5, %res4
Davx512-intrinsics-upgrade.ll21 %res4 = fadd <16 x float> %res2, %res3
22 ret <16 x float> %res4
42 %res4 = fadd <8 x double> %res2, %res3
43 ret <8 x double> %res4
62 %res4 = add <16 x i32> %res2, %res3
63 ret <16 x i32> %res4
82 %res4 = add <8 x i64> %res2, %res3
83 ret <8 x i64> %res4
102 %res4 = fadd <16 x float> %res2, %res3
103 ret <16 x float> %res4
[all …]
Davx512dq-intrinsics.ll345 %res4 = fadd <2 x double> %res2, %res3
346 ret <2 x double> %res4
365 %res4 = fadd <8 x float> %res2, %res3
366 ret <8 x float> %res4
385 %res4 = fadd <16 x float> %res2, %res3
386 ret <16 x float> %res4
405 %res4 = fadd <8 x double> %res3, %res2
406 ret <8 x double> %res4
425 %res4 = add <16 x i32> %res3, %res2
426 ret <16 x i32> %res4
[all …]
Davx512vl-intrinsics.ll42 %res4 = call i8 @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i32 4, i8 -1)
43 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
90 %res4 = call i8 @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i32 4, i8 %mask)
91 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
139 %res4 = call i8 @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i32 4, i8 -1)
140 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
187 %res4 = call i8 @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i32 4, i8 %mask)
188 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
236 %res4 = call i8 @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> %a0, <4 x i64> %a1, i32 4, i8 -1)
237 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
[all …]
Davx512bwvl-intrinsics-upgrade.ll20 %res4 = add <32 x i8> %res2, %res3
21 ret <32 x i8> %res4
40 %res4 = add <16 x i8> %res2, %res3
41 ret <16 x i8> %res4
60 %res4 = add <16 x i16> %res2, %res3
61 ret <16 x i16> %res4
80 %res4 = add <8 x i16> %res2, %res3
81 ret <8 x i16> %res4
100 %res4 = add <64 x i8> %res2, %res3
101 ret <64 x i8> %res4
[all …]
Davx512-intrinsics.ll417 %res4 = add i64 %res3, %res2
418 ret i64 %res4
436 %res4 = add i64 %res3, %res2
437 ret i64 %res4
455 %res4 = add i64 %res3, %res2
456 ret i64 %res4
474 %res4 = add i64 %res3, %res2
475 ret i64 %res4
493 %res4 = add i32 %res3, %res2
494 ret i32 %res4
[all …]
Davx512vl-intrinsics-upgrade.ll21 %res4 = add <8 x i32> %res2, %res3
22 ret <8 x i32> %res4
41 %res4 = add <4 x i32> %res2, %res3
42 ret <4 x i32> %res4
61 %res4 = add <4 x i64> %res2, %res3
62 ret <4 x i64> %res4
81 %res4 = add <2 x i64> %res2, %res3
82 ret <2 x i64> %res4
101 %res4 = fadd <4 x double> %res2, %res3
102 ret <4 x double> %res4
[all …]
/external/icu/icu4c/source/test/intltest/
Dnmfmapts.cpp124 UnicodeString res1, res2, res3, res4, res5, res6; in testAPI() local
136 res4 = cur_fr->format(l, res4, pos2); in testAPI()
137 logln((UnicodeString) "" + (int32_t) l + " formatted to " + res4); in testAPI()
332 UnicodeString res0, res1, res2, res3, res4, res5; in testRegistration() local
341 f4->format(n, res4); in testRegistration()
352 logln((UnicodeString)"f4 reg int: " + res4); in testRegistration()
368 if (res4 != res1) { in testRegistration()
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c266 v8i16 vec, res0, res1, res2, res3, res4, res5, res6, res7; in vpx_idct16x16_1_add_msa() local
277 UNPCK_UB_SH(dst0, res0, res4); in vpx_idct16x16_1_add_msa()
282 ADD4(res4, vec, res5, vec, res6, vec, res7, vec, res4, res5, res6, res7); in vpx_idct16x16_1_add_msa()
284 CLIP_SH4_0_255(res4, res5, res6, res7); in vpx_idct16x16_1_add_msa()
285 PCKEV_B4_UB(res4, res0, res5, res1, res6, res2, res7, res3, tmp0, tmp1, in vpx_idct16x16_1_add_msa()
330 v8i16 res0, res1, res2, res3, res4, res5, res6, res7; in vpx_iadst16_1d_columns_addblk_msa() local
419 ILVR_B2_SH(zero, dst4, zero, dst5, res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
420 ADD2(res4, out4, res5, out5, res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
421 CLIP_SH2_0_255(res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
422 PCKEV_B2_SH(res4, res4, res5, res5, res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
[all …]
Dvpx_convolve8_avg_horiz_msa.c485 v8u16 res0, res1, res2, res3, res4, res5, res6, res7, filt; in common_hz_2t_and_aver_dst_16w_msa() local
503 DOTP_UB4_UH(vec4, vec5, vec6, vec7, filt0, filt0, filt0, filt0, res4, res5, in common_hz_2t_and_aver_dst_16w_msa()
506 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_16w_msa()
512 PCKEV_AVG_ST_UB(res5, res4, dst2, dst); in common_hz_2t_and_aver_dst_16w_msa()
528 DOTP_UB4_UH(vec4, vec5, vec6, vec7, filt0, filt0, filt0, filt0, res4, res5, in common_hz_2t_and_aver_dst_16w_msa()
531 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_16w_msa()
537 PCKEV_AVG_ST_UB(res5, res4, dst2, dst); in common_hz_2t_and_aver_dst_16w_msa()
552 v8u16 res0, res1, res2, res3, res4, res5, res6, res7, filt; in common_hz_2t_and_aver_dst_32w_msa() local
578 DOTP_UB4_UH(vec4, vec5, vec6, vec7, filt0, filt0, filt0, filt0, res4, res5, in common_hz_2t_and_aver_dst_32w_msa()
581 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_32w_msa()
[all …]
/external/mesa3d/src/gallium/drivers/softpipe/
Dsp_quad_blend.c158 uint *res4 = (uint *) res; in logicop_quad() local
178 res4[j] = 0; in logicop_quad()
182 res4[j] = ~(src4[j] | dst4[j]); in logicop_quad()
186 res4[j] = ~src4[j] & dst4[j]; in logicop_quad()
190 res4[j] = ~src4[j]; in logicop_quad()
194 res4[j] = src4[j] & ~dst4[j]; in logicop_quad()
198 res4[j] = ~dst4[j]; in logicop_quad()
202 res4[j] = dst4[j] ^ src4[j]; in logicop_quad()
206 res4[j] = ~(src4[j] & dst4[j]); in logicop_quad()
210 res4[j] = src4[j] & dst4[j]; in logicop_quad()
[all …]
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/format/
DIntlTestNumberFormatAPI.java87 StringBuffer res4 = new StringBuffer(); in TestAPI() local
104 res4 = cur_fr.format(l, res4, pos2); in TestAPI()
105 logln("" + l + " formatted to " + res4); in TestAPI()
DIntlTestDecimalFormatAPI.java146 StringBuffer res4 = new StringBuffer(); in TestAPI() local
161 res4 = cust1.format(l, res4, pos4); in TestAPI()
162 logln("" + l + " formatted to " + res4); in TestAPI()
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/format/
DIntlTestNumberFormatAPI.java86 StringBuffer res4 = new StringBuffer(); in TestAPI() local
103 res4 = cur_fr.format(l, res4, pos2); in TestAPI()
104 logln("" + l + " formatted to " + res4); in TestAPI()
DIntlTestDecimalFormatAPI.java145 StringBuffer res4 = new StringBuffer(); in TestAPI() local
160 res4 = cust1.format(l, res4, pos4); in TestAPI()
161 logln("" + l + " formatted to " + res4); in TestAPI()
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll84 %res4 = zext <8 x i1> %res4_i1 to <8 x i16>
85 ret <8 x i16> %res4
141 %res4 = zext <16 x i1> %res4_i1 to <16 x i8>
142 ret <16 x i8> %res4
248 %res4 = insertelement <8 x i16> %vec, i16 %elt, i32 4
249 ret <8 x i16> %res4
303 %res4 = insertelement <16 x i8> %vec, i8 %elt, i32 4
304 ret <16 x i8> %res4
429 %res4 = zext i1 %res4_i1 to i64
430 ret i64 %res4
[all …]
/external/libyuv/files/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
144 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
229 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeUVWx16_MSA()

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