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/external/llvm/test/MC/Mips/
Drotations32.s25 # CHECK-32R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
28 # CHECK-32R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
33 # CHECK-32R: rotr $4, $4, 31 # encoding: [0x00,0x24,0x27,0xc2]
38 # CHECK-32R: rotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xc2]
43 # CHECK-32R: rotr $4, $4, 30 # encoding: [0x00,0x24,0x27,0x82]
48 # CHECK-32R: rotr $4, $5, 30 # encoding: [0x00,0x25,0x27,0x82]
64 # CHECK-32R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
67 # CHECK-32R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
72 # CHECK-32R: rotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x42]
77 # CHECK-32R: rotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x42]
[all …]
Dset-mips0-directive.s5 rotr $7, $7, 22
10 rotr $2, $2, 15
15 rotr $3, $3, 19
17 # CHECK: rotr $7, $7, 22
22 # CHECK: rotr $2, $2, 15
27 # CHECK: rotr $3, $3, 19
Dset-mips-directives.s19 rotr $2,15
22 rotr $2,15
25 rotr $2,15
55 # CHECK: rotr $2, $2, 15
58 # CHECK: rotr $2, $2, 15
61 # CHECK: rotr $2, $2, 15
Drotations64.s25 # CHECK-64R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
28 # CHECK-64R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
33 # CHECK-64R: rotr $4, $4, 31 # encoding: [0x00,0x24,0x27,0xc2]
38 # CHECK-64R: rotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xc2]
43 # CHECK-64R: rotr $4, $4, 30 # encoding: [0x00,0x24,0x27,0x82]
48 # CHECK-64R: rotr $4, $5, 30 # encoding: [0x00,0x25,0x27,0x82]
64 # CHECK-64R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
67 # CHECK-64R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
72 # CHECK-64R: rotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x42]
77 # CHECK-64R: rotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x42]
[all …]
Dset-arch.s18 rotr $2, $2, 15
21 rotr $2, $2, 15
24 rotr $2, $2, 15
57 # CHECK: rotr $2, $2, 15
Dmicromips-shift-instructions.s16 # CHECK-EL: rotr $9, $6, 7 # encoding: [0x26,0x01,0xc0,0x38]
36 # CHECK-EB: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
53 rotr $9, $6, 7
Dmips-alu-instructions.s19 # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
50 rotr $9, $6, 7
Dmips64-alu-instructions.s17 # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
45 rotr $9, $6, 7
/external/llvm/test/CodeGen/Mips/
Dbswap.ll9 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
13 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
36 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
38 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
76 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
78 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
80 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
82 ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
86 ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
88 ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
[all …]
Drotate.ll22 ; CHECK: rotr $2, $4, 22
24 ; MM32: rotr $2, $4, 22
45 ; CHECK: rotr $2, $4, 10
47 ; MM32: rotr $2, $4, 10
/external/wpa_supplicant_8/src/crypto/
Daes_i.h70 static inline u32 rotr(u32 val, int bits) in rotr() function
76 #define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
77 #define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
78 #define TE3(i) rotr(Te0[(i) & 0xff], 24)
94 #define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
95 #define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
96 #define TD3(i) rotr(Td0[(i) & 0xff], 24)
102 #define TD1_(i) rotr(Td0[(i) & 0xff], 8)
103 #define TD2_(i) rotr(Td0[(i) & 0xff], 16)
104 #define TD3_(i) rotr(Td0[(i) & 0xff], 24)
/external/swiftshader/third_party/LLVM/test/TableGen/
DSetTheory.td115 // The 'rotr' operator rotates right, but also accepts a negative shift.
116 def rotr;
117 def S7a : Set<(rotr S0f, 0)>;
118 def S7b : Set<(rotr S0f, 1)>;
119 def S7c : Set<(rotr S0f, 3)>;
120 def S7d : Set<(rotr S0f, 4)>;
121 def S7e : Set<(rotr S0f, 5)>;
122 def S7f : Set<(rotr S0f, -1)>;
123 def S7g : Set<(rotr S0f, -4)>;
124 def S7h : Set<(rotr S0f, -5)>;
/external/llvm/test/TableGen/
DSetTheory.td115 // The 'rotr' operator rotates right, but also accepts a negative shift.
116 def rotr;
117 def S7a : Set<(rotr S0f, 0)>;
118 def S7b : Set<(rotr S0f, 1)>;
119 def S7c : Set<(rotr S0f, 3)>;
120 def S7d : Set<(rotr S0f, 4)>;
121 def S7e : Set<(rotr S0f, 5)>;
122 def S7f : Set<(rotr S0f, -1)>;
123 def S7g : Set<(rotr S0f, -4)>;
124 def S7h : Set<(rotr S0f, -5)>;
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Drotate.ll13 ; CHECK: rotr $2, $4, 22
32 ; CHECK: rotr $2, $4, 10
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td40 defm ROTR : BinaryInt<rotr, "rotr">;
70 def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>;
72 def : Pat<(rotr I64:$lhs, (and I64:$rhs, 63)), (ROTR_I64 I64:$lhs, I64:$rhs)>;
/external/llvm/test/CodeGen/AArch64/
Darm64-regress-interphase-shift.ll5 ; unselectable "rotr" node: (i32 (rotr i32, i64)).
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td508 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
511 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
514 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
517 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
522 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
525 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
529 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
533 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
538 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
541 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
[all …]
/external/skia/bench/
DFontCacheBench.cpp56 static uint32_t rotr(uint32_t value, unsigned bits) { in rotr() function
103 if (false) rotr(0, 0); in FontCacheEfficiency()
/external/llvm/unittests/ADT/
DAPIntTest.cpp172 EXPECT_EQ(one, one.rotr(0)); in TEST()
173 EXPECT_EQ(one, one.rotr(1)); in TEST()
812 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(0)); in TEST()
813 EXPECT_EQ(APInt(8, 8), APInt(8, 16).rotr(1)); in TEST()
814 EXPECT_EQ(APInt(8, 4), APInt(8, 16).rotr(2)); in TEST()
815 EXPECT_EQ(APInt(8, 1), APInt(8, 16).rotr(4)); in TEST()
816 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(8)); in TEST()
818 EXPECT_EQ(APInt(8, 1), APInt(8, 1).rotr(0)); in TEST()
819 EXPECT_EQ(APInt(8, 128), APInt(8, 1).rotr(1)); in TEST()
820 EXPECT_EQ(APInt(8, 64), APInt(8, 1).rotr(2)); in TEST()
[all …]
/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips64r218433 rotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
18434 rotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
18435 rotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
18436 rotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
18437 rotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
18438 rotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
18439 rotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
18440 rotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
18441 rotr $t0, $t1, 0x00 :: rt 0x9823b6e, rs 0x9823b6e, imm 0x0000
18442 rotr $t2, $t3, 0x1f :: rt 0x130476dc, rs 0x9823b6e, imm 0x001f
[all …]
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td580 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
583 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
586 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
589 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
594 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
597 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
601 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
606 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
612 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
616 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
[all …]
/external/llvm/test/CodeGen/WebAssembly/
Di32.ll230 ; CHECK-LABEL: rotr:
233 ; CHECK-NEXT: i32.rotr $push0=, $0, $1
235 define i32 @rotr(i32 %x, i32 %y) {
246 ; CHECK-NEXT: i32.rotr $push0=, $0, $1
Di64.ll230 ; CHECK-LABEL: rotr:
233 ; CHECK-NEXT: i64.rotr $push0=, $0, $1
235 define i64 @rotr(i64 %x, i64 %y) {
246 ; CHECK-NEXT: i64.rotr $push0=, $0, $1
/external/llvm/test/MC/Mips/micromips/
Dinvalid.s42 rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
43 rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
44 rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
45 rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s26 …rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
27 …rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…

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