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Searched refs:rotrv (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Drotate.ll8 ; CHECK: rotrv $2, $4
12 ; MM32: rotrv $2, $4, $2
33 ; CHECK: rotrv $2, $4, $5
35 ; MM32: rotrv $2, $4, $5
/external/llvm/test/MC/Mips/
Drotations32.s15 # CHECK-32R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46]
22 # CHECK-32R: rotrv $4, $5, $4 # encoding: [0x00,0x85,0x20,0x46]
55 # CHECK-32R: rotrv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x46]
61 # CHECK-32R: rotrv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x46]
Dmicromips-shift-instructions.s17 # CHECK-EL: rotrv $9, $6, $7 # encoding: [0xc7,0x00,0xd0,0x48]
37 # CHECK-EB: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
54 rotrv $9, $6, $7
Drotations64.s15 # CHECK-64R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46]
22 # CHECK-64R: rotrv $4, $5, $4 # encoding: [0x00,0x85,0x20,0x46]
55 # CHECK-64R: rotrv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x46]
61 # CHECK-64R: rotrv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x46]
Dmips-alu-instructions.s20 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
51 rotrv $9, $6, $7
Dmips64-alu-instructions.s18 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
46 rotrv $9, $6, $7
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Drotate.ll3 ; CHECK: rotrv $2, $4
22 ; CHECK: rotrv $2, $4, $5
/external/valgrind/none/tests/mips32/
DMIPS32int.stdout.exp-mips32r2-BE1033 rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
1034 rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1035 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1036 rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1037 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1038 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1039 rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1040 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1041 rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1042 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-LE1033 rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
1034 rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1035 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1036 rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1037 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1038 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1039 rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1040 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1041 rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1042 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s28 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64r2.s36 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32/
Dinvalid-mips32r2.s30 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s168 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s169 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s168 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s235 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s235 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s236 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips64r219457 rotrv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
19458 rotrv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
19459 rotrv $t0, $t1, $t2 :: rd 0x608edb82, rs 0x9823b6e, rt 0xffffffffb8757bda
19460 rotrv $t0, $t1, $t2 :: rd 0x36c86a19, rs 0xd4326d9, rt 0xffffffffbcb4666d
19461 rotrv $t0, $t1, $t2 :: rd 0xffffffffdc130476, rs 0x130476dc, rt 0xffffffffa2f33668
19462 rotrv $t0, $t1, $t2 :: rd 0x2f8ad6d6, rs 0x17c56b6b, rt 0xffffffffa6322bdf
19463 rotrv $t0, $t1, $t2 :: rd 0xffffffffc86a1936, rs 0x1a864db2, rt 0xffffffffab710d06
19464 rotrv $t0, $t1, $t2 :: rd 0xffffffffa8028f23, rs 0x1e475005, rt 0xffffffffafb010b1
19465 rotrv $t0, $t1, $t2 :: rd 0xffffffffdb82608e, rs 0x2608edb8, rt 0xffffffff97ffad0c
19466 rotrv $t0, $t1, $t2 :: rd 0x593e01e4, rs 0x22c9f00f, rt 0xffffffff933eb0bb
[all …]
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32r2.s62 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/micromips64r6/
Dvalid.s48 …rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x…
/external/llvm/test/MC/Mips/micromips/
Dinvalid.s46 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/micromips32r6/
Dvalid.s87 …rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x…
/external/llvm/test/MC/Disassembler/Mips/micromips32r3/
Dvalid.txt89 0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
Dvalid-el.txt89 0xc7 0x00 0xd0 0x48 # CHECK: rotrv $9, $6, $7

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