Searched refs:rr0 (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitTracker.cpp | 188 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs) in evaluate() local
253 return rr0(eIMM(im(1), W0), Outputs); in evaluate()
255 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); in evaluate()
257 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); in evaluate()
265 return rr0(RC, Outputs); in evaluate()
273 return rr0(rc(1), Outputs); in evaluate()
281 return rr0(RC, Outputs); in evaluate()
286 return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs); in evaluate()
301 return rr0(RC, Outputs); in evaluate()
305 return rr0(eADD(rc(1), rc(2)), Outputs); in evaluate()
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 1613 def : InstRW<[WriteFVarBlend], (instregex "BLENDVP(S|D)rr0")>;
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| D | X86InstrSSE.td | 7165 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrSSE.td | 5978 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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