Searched refs:rscs (Results 1 – 12 of 12) sorted by relevance
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-const-a32.cc | 67 M(rscs) \
|
| D | test-assembler-cond-rd-rn-operand-rm-a32.cc | 67 M(rscs) \
|
| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 67 M(rscs) \
|
| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 67 M(rscs) \
|
| D | test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 67 M(rscs) \
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1385 rscs r1, r8, #4064
1411 @ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2885 void rscs(Condition cond, Register rd, Register rn, const Operand& operand);
2886 void rscs(Register rd, Register rn, const Operand& operand) { in rscs() function
2887 rscs(al, rd, rn, operand); in rscs()
|
| D | disasm-aarch32.h | 917 void rscs(Condition cond, Register rd, Register rn, const Operand& operand);
|
| D | disasm-aarch32.cc | 2364 void Disassembler::rscs(Condition cond, in rscs() function in vixl::aarch32::Disassembler
59356 rscs(condition, in DecodeA32()
59375 rscs(condition, in DecodeA32()
60601 rscs(condition, in DecodeA32()
61767 rscs(condition, Register(rd), Register(rn), imm); in DecodeA32()
|
| D | assembler-aarch32.cc | 8519 void Assembler::rscs(Condition cond, in rscs() function in vixl::aarch32::Assembler
8567 Delegate(kRscs, &Assembler::rscs, cond, rd, rn, operand); in rscs()
|
| D | macro-assembler-aarch32.h | 3372 rscs(cond, rd, rn, operand); in Rscs()
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2076 rscs r1, r8, #4064
2120 @ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2]
|