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/external/llvm/test/MC/AArch64/
Dneon-scalar-saturating-add-sub.s8 sqadd s20, s21, s2
21 uqadd s20, s21, s2
34 sqsub s20, s21, s2
47 uqsub s20, s21, s2
61 suqadd s21, s12
75 usqadd s21, s12
Dneon-scalar-saturating-shift.s8 sqshl s20, s21, s2
21 uqshl s20, s21, s2
Dneon-scalar-saturating-rounding-shift.s8 sqrshl s20, s21, s2
21 uqrshl s20, s21, s2
Dneon-scalar-recip.s10 frecps s21, s16, s13
22 frsqrts s21, s5, s12
Dneon-scalar-mul.s10 sqdmulh s20, s21, s2
20 sqrdmulh s20, s21, s2
Dneon-scalar-cvt.s58 fcvtzs s21, s12, #1
70 fcvtzu s21, s12, #1
Dneon-scalar-by-elem-mul.s30 fmulx s13, s21, v10.s[3]
/external/bison/lib/
Dstreq.h139 streq1 (const char *s1, const char *s2, char s21, char s22, char s23, char s24, char s25, char s26,… in streq1() argument
141 if (s1[1] == s21) in streq1()
143 if (s21 == 0) in streq1()
153 streq0 (const char *s1, const char *s2, char s20, char s21, char s22, char s23, char s24, char s25,… in streq0() argument
160 return streq1 (s1, s2, s21, s22, s23, s24, s25, s26, s27, s28); in streq0()
166 #define STREQ_OPT(s1,s2,s20,s21,s22,s23,s24,s25,s26,s27,s28) \ argument
167 streq0 (s1, s2, s20, s21, s22, s23, s24, s25, s26, s27, s28)
171 #define STREQ_OPT(s1,s2,s20,s21,s22,s23,s24,s25,s26,s27,s28) \ argument
Dc-strcaseeq.h149 strcaseeq1 (const char *s1, const char *s2, char s21, char s22, char s23, char s24, char s25, char … in strcaseeq1() argument
151 if (CASEEQ (s1[1], s21)) in strcaseeq1()
153 if (s21 == 0) in strcaseeq1()
163 strcaseeq0 (const char *s1, const char *s2, char s20, char s21, char s22, char s23, char s24, char … in strcaseeq0() argument
170 return strcaseeq1 (s1, s2, s21, s22, s23, s24, s25, s26, s27, s28); in strcaseeq0()
176 #define STRCASEEQ(s1,s2,s20,s21,s22,s23,s24,s25,s26,s27,s28) \ argument
177 strcaseeq0 (s1, s2, s20, s21, s22, s23, s24, s25, s26, s27, s28)
181 #define STRCASEEQ(s1,s2,s20,s21,s22,s23,s24,s25,s26,s27,s28) \ argument
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dvmls.ll12 ; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
17 ; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
22 ; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
27 ; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
37 ; ASM: vmls.f32 s21, s20, s22
Dvmla.ll12 ; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
17 ; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
22 ; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
27 ; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
37 ; ASM: vmla.f32 s21, s20, s22
Dvpush.ll31 ; ASM: vpush {s18, s19, s20, s21}
39 ; ASM: vpop {s18, s19, s20, s21}
/external/valgrind/none/tests/arm/
Dvfp.c1168 … TESTINSN_bin_f32("vmla.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
1174 …TESTINSN_bin_f32("vmla.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.29456… in main()
1218 …TESTINSN_bin_f32("vnmla.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
1224 …TESTINSN_bin_f32("vnmla.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945… in main()
1268 … TESTINSN_bin_f32("vmls.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
1274 …TESTINSN_bin_f32("vmls.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.29456… in main()
1318 …TESTINSN_bin_f32("vnmls.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
1324 …TESTINSN_bin_f32("vnmls.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945… in main()
1368 … TESTINSN_bin_f32("vmul.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
1374 …TESTINSN_bin_f32("vmul.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.29456… in main()
[all …]
Dvfp.stdout.exp637 vcvt.u32.f32 s19, s21 :: Sd 0x00000000 Sm (i32)0xc0e33333
649 vcvt.s32.f32 s20, s21 :: Sd 0x7fffffff Sm (i32)0x64cb49b4
689 vcvt.f64.u32 d30, s21 :: Dd 0x5c200000 41e88483 Sm 0xc4241ae1
697 vcvt.f64.s32 d30, s21 :: Dd 0x8f800000 c1cdedf2 Sm 0xc4241ae1
706 vcvt.f64.f32 d29, s21 :: Dd 0x406d54cc 0xc0000000 Sm 0x436aa666
712 vcvt.f64.f32 d9, s21 :: Dd 0x7ff80000 0x00000000 Sm 0x7fc00000
838 vcmp.f32 s21 :: FPSCR 0x80000000 Sd 0xc58d6400
847 vcmp.f32 s21 :: FPSCR 0x80000000 Sd 0xff800000
855 vcmpe.f32 s21 :: FPSCR 0x80000000 Sd 0xc58d6400
864 vcmpe.f32 s21 :: FPSCR 0x80000000 Sd 0xff800000
[all …]
Dvfpv4_fma.c120 … TESTINSN_bin_f32("vfma.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
126 …TESTINSN_bin_f32("vfma.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.29456… in main()
170 … TESTINSN_bin_f32("vfms.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
176 …TESTINSN_bin_f32("vfms.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.29456… in main()
220 …TESTINSN_bin_f32("vfnma.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
226 …TESTINSN_bin_f32("vfnma.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945… in main()
270 …TESTINSN_bin_f32("vfnms.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); in main()
276 …TESTINSN_bin_f32("vfnms.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945… in main()
/external/clang/test/CodeGenCXX/
Dcatch-undef-behavior.cpp488 S2 s21; in test2() local
489 callee2(s21); in test2()
491 s22 = s21; in test2()
/external/clang/test/CodeGen/
Darm-arguments.c121 struct s21 { struct {} f1; int f0 : 4; }; argument
122 struct s21 f21(void) {} in f21()
/external/clang/test/Sema/
Dbitfield-layout_1.c201 } s21; variable
202 CHECK_SIZE(s21,10)
/external/boringssl/src/ssl/test/runner/ed25519/internal/edwards25519/
Dedwards25519.go1084 s21 := a10*b11 + a11*b10
1119 s21 += carry[20]
1155 carry[21] = (s21 + (1 << 20)) >> 21
1157 s21 -= carry[21] << 21
1175 s9 += s21 * 666643
1176 s10 += s21 * 470296
1177 s11 += s21 * 654183
1178 s12 -= s21 * 997805
1179 s13 += s21 * 136657
1180 s14 -= s21 * 683901
[all …]
/external/swiftshader/third_party/subzero/src/
DIceRegistersARM32.def58 X(Reg_s21, 21, "s21", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s21, d10, q5)) \
82 X(Reg_d10, 10, "d10", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d10, q5, s20, s21)) \
112 …X(Reg_q5, 5, "q5", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q5, d10, d11, s20, s21, s22…
/external/llvm/test/MC/Disassembler/ARM/
Dfp-encoding.txt218 # CHECK: vstmiaeq r0, {s19, s20, s21, s22, s23}
220 # CHECK: vldmiaeq r3, {s18, s19, s20, s21, s22, s23}
229 # CHECK: vldmdbeq r5!, {s21, s22, s23}
252 # CHECK: vldmiaeq r8!, {s21, s22, s23}
/external/llvm/test/CodeGen/AArch64/
Dremat-float0.ll15 …0},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s2…
/external/boringssl/src/crypto/curve25519/
Dcurve25519.c3814 int64_t s21 = 2097151 & (load_3(s + 55) >> 1); in x25519_sc_reduce() local
3851 s9 += s21 * 666643; in x25519_sc_reduce()
3852 s10 += s21 * 470296; in x25519_sc_reduce()
3853 s11 += s21 * 654183; in x25519_sc_reduce()
3854 s12 -= s21 * 997805; in x25519_sc_reduce()
3855 s13 += s21 * 136657; in x25519_sc_reduce()
3856 s14 -= s21 * 683901; in x25519_sc_reduce()
3857 s21 = 0; in x25519_sc_reduce()
4192 int64_t s21; in sc_muladd() local
4249 s21 = a10 * b11 + a11 * b10; in sc_muladd()
[all …]
/external/llvm/test/MC/ARM/
Dthumb-fp-armv8.s79 vselvs.f32 s21, s16, s14
80 @ CHECK: vselvs.f32 s21, s16, s14 @ encoding: [0x58,0xfe,0x07,0xaa]
Dfp-armv8.s76 vselvs.f32 s21, s16, s14
77 @ CHECK: vselvs.f32 s21, s16, s14 @ encoding: [0x07,0xaa,0x58,0xfe]

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