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Searched refs:s_add_i32 (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dadd.ll66 ; SI: s_add_i32
67 ; SI: s_add_i32
68 ; SI: s_add_i32
69 ; SI: s_add_i32
70 ; SI: s_add_i32
71 ; SI: s_add_i32
72 ; SI: s_add_i32
73 ; SI: s_add_i32
99 ; SI: s_add_i32
100 ; SI: s_add_i32
[all …]
Dgep-address-space.ll18 ; CI: s_add_i32
27 ; SI: s_add_i32
28 ; SI: s_add_i32
29 ; SI: s_add_i32
30 ; SI: s_add_i32
56 ; SI: s_add_i32
57 ; SI: s_add_i32
D32-bit-local-address-space.ll24 ; SI: s_add_i32 [[SPTR:s[0-9]]]
48 ; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
72 ; SI-NEXT: s_add_i32
111 ; SI: s_add_i32 [[SADDR:s[0-9]+]],
132 ; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
Dsminmax.ll7 ; GCN: s_add_i32
38 ; GCN: s_add_i32
39 ; GCN: s_add_i32
89 ; GCN: s_add_i32
90 ; GCN: s_add_i32
91 ; GCN: s_add_i32
92 ; GCN: s_add_i32
Ds_addk_i32.ll19 ; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]]
20 ; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]]
87 ; SI: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8000{{$}}
Dshl_add_constant.ll60 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], [[Y]]
76 ; SI: s_add_i32 [[TMP:s[0-9]+]], [[Y]], [[SHL3]]
77 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
Dindirect-addressing-si.ll59 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
71 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
85 ; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
143 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
158 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
171 ; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
186 ; CHECK: s_add_i32 m0, m0, -{{[0-9]+}}
399 ; CHECK-DAG: s_add_i32 m0, [[ARG]], -16
402 ; CHECK: s_add_i32 m0, [[ARG]], -14
443 ; CHECK: s_add_i32 m0, [[IDX]], 4
Dsgpr-control-flow.ll38 ; SI: s_add_i32 [[SGPR:s[0-9]+]]
39 ; SI-NOT: s_add_i32 [[SGPR]]
Dcaptured-frame-index.ll143 ; GCN: s_add_i32 [[BASE_1_OFF_0:s[0-9]+]], 0, 0x3ffc
149 ; GCN: s_add_i32 [[BASE_1_OFF_1:s[0-9]+]], 0, 56
Dctpop64.ll148 ; GCN: s_add_i32 s{{[0-9]+}}, [[SRESULT1]], [[SRESULT0]]
161 ; GCN: s_add_i32 {{s[0-9]+}}, [[REG0]], [[REG1]]
Dadd_i64.ll75 ; SI: s_add_i32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]]
Duaddo.ll26 ; SI: s_add_i32
Dfceil64.ll16 ; SI-DAG: s_add_i32 [[SEXP1:s[0-9]+]], [[SEXP]], 0xfffffc01
Dftrunc.f64.ll28 ; SI-DAG: s_add_i32 [[SEXP1:s[0-9]+]], [[SEXP]], 0xfffffc01
Dret.ll184 ; GCN: s_add_i32 s0, s3, 2
213 ; GCN-DAG: s_add_i32 s0, s3, 2
Dlocal-64.ll39 ; CI: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
Dsext-in-reg.ll25 ; SI: s_add_i32 [[VAL:s[0-9]+]],
43 ; SI: s_add_i32 [[VAL:s[0-9]+]],
61 ; SI: s_add_i32 [[VAL:s[0-9]+]],
Dand.ll83 ; SI: s_add_i32
84 ; SI: s_add_i32 [[ADD:s[0-9]+]], s{{[0-9]+}}, [[K]]
Dctlz.ll117 ; SI-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32
Dctlz_zero_undef.ll97 ; SI-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32
Duniform-cfg.ll285 ; get s_add_i32 here.
/external/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s4 s_add_i32 s104, s0, s1 label
7 s_add_i32 s105, s0, s1 label
Dsop2.s13 s_add_i32 s1, s2, s3 label
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td198 defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32",