| /external/llvm/test/MC/AMDGPU/ |
| D | out-of-range-registers.s | 25 s_load_dwordx4 s[102:105], s[2:3], s4 label
28 s_load_dwordx4 s[104:108], s[2:3], s4 label
31 s_load_dwordx4 s[108:112], s[2:3], s4 label
34 s_load_dwordx4 s[1:4], s[2:3], s4 label
37 s_load_dwordx4 s[1:4], s[2:3], s4 label
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| D | smrd.s | 47 s_load_dwordx4 s[4:7], s[2:3], 1 label
51 s_load_dwordx4 s[4:7], s[2:3], s4 label
55 s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 label
59 s_load_dwordx4 s[100:103], s[2:3], s4 label
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| D | smrd-err.s | 4 s_load_dwordx4 s[100:103], s[2:3], s4 label
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| D | reg-syntax-extra.s | 73 s_load_dwordx4 [ttmp4,ttmp5,ttmp6,ttmp7], [ttmp2,ttmp3], ttmp4 label
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | wait.ll | 8 ; DEFAULT: s_load_dwordx4
9 ; DEFAULT: s_load_dwordx4
38 ; ILPMAX: s_load_dwordx4
41 ; ILPMAX: s_load_dwordx4
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| D | inline-constraints.ll | 10 ; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
20 …%s128 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
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| D | reduce-store-width-alignment.ll | 13 ; GCN: s_load_dwordx4
32 ; GCN: s_load_dwordx4
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| D | kernel-args.ll | 167 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
168 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
179 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
180 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
222 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
223 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
235 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
236 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
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| D | load-constant-i32.ll | 29 ; GCN: s_load_dwordx4
40 ; GCN: s_load_dwordx4
154 ; GCN: s_load_dwordx4
166 ; GCN: s_load_dwordx4
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| D | select-vectors.ll | 113 ; SI: s_load_dwordx4
114 ; SI: s_load_dwordx4
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| D | load-constant-i64.ll | 17 ; GCN: s_load_dwordx4
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| D | si-scheduler.ll | 12 ; CHECK: s_load_dwordx4
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| D | load-constant-i16.ll | 53 ; GCN: s_load_dwordx4
217 ; GCN: s_load_dwordx4
228 ; GCN: s_load_dwordx4
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| D | unaligned-load-store.ll | 463 ; SI: s_load_dwordx4
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| D | insert_vector_elt.ll | 13 ; GCN: s_load_dwordx4
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| D | indirect-addressing-si.ll | 260 ; CHECK-DAG: s_load_dwordx4 s{{\[}}[[S_ELT0:[0-9]+]]:[[S_ELT3:[0-9]+]]{{\]}}
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| D | load-constant-i8.ll | 65 ; GCN: s_load_dwordx4
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| D | llvm.SI.gather4.ll | 470 ;CHECK: s_load_dwordx4 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
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| /external/llvm/test/Object/AMDGPU/ |
| D | objdump.s | 32 s_load_dwordx4 s[8:11], s[4:5], 0x40
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | smrd_vi.txt | 21 # VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
24 # VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 49 defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
|