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Searched refs:s_load_dwordx8 (Results 1 – 11 of 11) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s40 s_load_dwordx8 s[104:111], s[2:3], s4 label
43 s_load_dwordx8 s[100:107], s[2:3], s4 label
46 s_load_dwordx8 s[108:115], s[2:3], s4 label
Dsmrd.s63 s_load_dwordx8 s[8:15], s[2:3], 1 label
67 s_load_dwordx8 s[8:15], s[2:3], s4 label
71 s_load_dwordx8 s[96:103], s[2:3], s4 label
Dsmrd-err.s9 s_load_dwordx8 s[96:103], s[2:3], s4 label
/external/llvm/test/CodeGen/AMDGPU/
Dinline-constraints.ll11 ; GCN: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
21 …%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
Dload-constant-i64.ll28 ; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
40 ; GCN: s_load_dwordx8
Dload-constant-i32.ll51 ; GCN: s_load_dwordx8
183 ; GCN: s_load_dwordx8
202 ; GCN: s_load_dwordx8
Dsi-scheduler.ll13 ; CHECK: s_load_dwordx8
Dload-constant-i16.ll64 ; GCN: s_load_dwordx8
239 ; GCN: s_load_dwordx8
250 ; GCN: s_load_dwordx8
Dkernel-args.ll297 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
298 ; VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
314 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsmrd_vi.txt27 # VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
30 # VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td50 defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;