| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | xtype_complex.txt | 6 # CHECK: r17:16 = vxaddsubh(r21:20, r31:30):sat
8 # CHECK: r17:16 = vxsubaddh(r21:20, r31:30):sat
10 # CHECK: r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat
12 # CHECK: r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat
16 # CHECK: r17:16 = vxaddsubw(r21:20, r31:30):sat
18 # CHECK: r17:16 = vxsubaddw(r21:20, r31:30):sat
22 # CHECK: r17:16 = cmpy(r21, r31):sat
24 # CHECK: r17:16 = cmpy(r21, r31):<<1:sat
26 # CHECK: r17:16 = cmpy(r21, r31*):sat
28 # CHECK: r17:16 = cmpy(r21, r31*):<<1:sat
[all …]
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| D | xtype_mpy.txt | 30 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):sat
32 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:sat
34 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):sat
36 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:sat
38 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):rnd:sat
40 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:rnd:sat
42 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):rnd:sat
44 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:rnd:sat
46 # CHECK: r17:16 += vmpyweh(r21:20, r31:30):sat
48 # CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:sat
[all …]
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| D | xtype_alu.txt | 10 # CHECK: r17 = abs(r21):sat
30 # CHECK: r17:16 = add(r21:20, r31:30):sat
42 # CHECK: r17 = add(r21.l, r31.l):sat
44 # CHECK: r17 = add(r21.l, r31.h):sat
54 # CHECK: r17 = add(r21.l, r31.l):sat:<<16
56 # CHECK: r17 = add(r21.l, r31.h):sat:<<16
58 # CHECK: r17 = add(r21.h, r31.l):sat:<<16
60 # CHECK: r17 = add(r21.h, r31.h):sat:<<16
150 # CHECK: r17 = neg(r21):sat
154 # CHECK: r17 = round(r21:20):sat
[all …]
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| D | alu32_alu.txt | 10 # CHECK: r17 = add(r21, r31):sat
38 # CHECK: r17 = sub(r31, r21):sat
62 # CHECK: r17 = vaddh(r21, r31):sat
64 # CHECK: r17 = vadduh(r21, r31):sat
78 # CHECK: r17 = vsubh(r31, r21):sat
80 # CHECK: r17 = vsubuh(r31, r21):sat
|
| /external/stressapptest/src/ |
| D | main.cc | 21 Sat *sat = SatFactory(); in main() local
22 if (sat == NULL) { in main()
27 if (!sat->ParseArgs(argc, argv)) { in main()
29 sat->bad_status(); in main()
30 } else if (!sat->Initialize()) { in main()
32 sat->bad_status(); in main()
33 } else if (!sat->Run()) { in main()
35 sat->bad_status(); in main()
37 sat->PrintResults(); in main()
38 if (!sat->Cleanup()) { in main()
[all …]
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| /external/mesa3d/src/mesa/program/ |
| D | program_lexer.l | 163 sat (_SAT)?
183 ABS{sat} { return_opcode( 1, VECTOR_OP, ABS, 3); }
184 ADD{sat} { return_opcode( 1, BIN_OP, ADD, 3); }
187 CMP{sat} { return_opcode(require_ARB_fp, TRI_OP, CMP, 3); }
188 COS{sat} { return_opcode(require_ARB_fp, SCALAR_OP, COS, 3); }
190 DP3{sat} { return_opcode( 1, BIN_OP, DP3, 3); }
191 DP4{sat} { return_opcode( 1, BIN_OP, DP4, 3); }
192 DPH{sat} { return_opcode( 1, BIN_OP, DPH, 3); }
193 DST{sat} { return_opcode( 1, BIN_OP, DST, 3); }
195 EX2{sat} { return_opcode( 1, SCALAR_OP, EX2, 3); }
[all …]
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| /external/llvm/test/MC/Hexagon/ |
| D | v60-alu.s | 38 #CHECK: 1caeca00 { v1:0.h = vsub(v11:10.h,{{ *}}v15:14.h):sat }
39 v1:0.h=vsub(v11:10.h,v15:14.h):sat
41 #CHECK: 1ca8c43e { v31:30.w = vsub(v5:4.w,{{ *}}v9:8.w):sat }
42 v31:30.w=vsub(v5:4.w,v9:8.w):sat
50 #CHECK: 1c79c350 { v16.h = vsub(v3.h,{{ *}}v25.h):sat }
51 v16.h=vsub(v3.h,v25.h):sat
53 #CHECK: 1c7fd364 { v4.w = vsub(v19.w,{{ *}}v31.w):sat }
54 v4.w=vsub(v19.w,v31.w):sat
56 #CHECK: 1c67d816 { v22.ub = vsub(v24.ub,{{ *}}v7.ub):sat }
57 v22.ub=vsub(v24.ub,v7.ub):sat
[all …]
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| D | v60-vmpy1.s | 5 #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat }
6 v3.w=vdmpy(v3:2.h,r25.uh,#1):sat
8 #CHECK: 1936de0d { v13.w = vdmpy(v30.h,{{ *}}r22.uh):sat }
9 v13.w=vdmpy(v30.h,r22.uh):sat
53 #CHECK: 1925d86b { v11.w = vdmpy(v25:24.h,{{ *}}r5.h):sat }
54 v11.w=vdmpy(v25:24.h,r5.h):sat
56 #CHECK: 1925c255 { v21.w = vdmpy(v2.h,{{ *}}r5.h):sat }
57 v21.w=vdmpy(v2.h,r5.h):sat
59 #CHECK: 1941d424 { v4.h = vmpy(v20.h,{{ *}}r1.h):<<1:sat }
60 v4.h=vmpy(v20.h,r1.h):<<1:sat
[all …]
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| D | v60-vmpy-acc.s | 5 #CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat }
6 v23.w += vdmpy(v15:14.h,r22.uh,#1):sat
8 #CHECK: 193bf90f { v15.w += vdmpy(v25.h,r27.uh):sat }
9 v15.w += vdmpy(v25.h,r27.uh):sat
56 #CHECK: 1934fc62 { v2.w += vdmpy(v28.h,r20.h):sat }
57 v2.w += vdmpy(v28.h,r20.h):sat
59 #CHECK: 1925fe5f { v31.w += vdmpy(v31:30.h,r5.h):sat }
60 v31.w += vdmpy(v31:30.h,r5.h):sat
65 #CHECK: 1948e306 { v7:6.w += vmpy(v3.h,r8.h):sat }
66 v7:6.w += vmpy(v3.h,r8.h):sat
[all …]
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| D | v60-permute.s | 5 #CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat }
6 v15.b=vpack(v21.h,v18.h):sat
8 #CHECK: 1fd7d7a2 { v2.ub = vpack(v23.h{{ *}},{{ *}}v23.h):sat }
9 v2.ub=vpack(v23.h,v23.h):sat
17 #CHECK: 1fc9c5ed { v13.uh = vpack(v5.w{{ *}},{{ *}}v9.w):sat }
18 v13.uh=vpack(v5.w,v9.w):sat
20 #CHECK: 1ff1d81f { v31.h = vpack(v24.w{{ *}},{{ *}}v17.w):sat }
21 v31.h=vpack(v24.w,v17.w):sat
|
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | xtype_complex.ll | 13 ; CHECK: = vxaddsubh({{.*}}, {{.*}}):sat
20 ; CHECK: = vxsubaddh({{.*}}, {{.*}}):sat
27 ; CHECK: = vxaddsubh({{.*}}, {{.*}}):rnd:>>1:sat
34 ; CHECK: = vxsubaddh({{.*}}, {{.*}}):rnd:>>1:sat
42 ; CHECK: = vxaddsubw({{.*}}, {{.*}}):sat
49 ; CHECK: = vxsubaddw({{.*}}, {{.*}}):sat
57 ; CHECK: = cmpy({{.*}}, {{.*}}):sat
64 ; CHECK: = cmpy({{.*}}, {{.*}}):<<1:sat
71 ; CHECK: = cmpy({{.*}}, {{.*}}*):sat
78 ; CHECK: = cmpy({{.*}}, {{.*}}*):<<1:sat
[all …]
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| D | xtype_mpy.ll | 50 ; CHECK: = vmpyweh({{.*}}, {{.*}}):sat
57 ; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:sat
64 ; CHECK: = vmpywoh({{.*}}, {{.*}}):sat
71 ; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:sat
78 ; CHECK: = vmpyweh({{.*}}, {{.*}}):rnd:sat
85 ; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:rnd:sat
92 ; CHECK: = vmpywoh({{.*}}, {{.*}}):rnd:sat
99 ; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:rnd:sat
107 ; CHECK: = vmpyweuh({{.*}}, {{.*}}):sat
114 ; CHECK: = vmpyweuh({{.*}}, {{.*}}):<<1:sat
[all …]
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| D | xtype_alu.ll | 29 ; CHECK: = abs({{.*}}):sat
87 ; CHECK: = add({{.*}}, {{.*}}):sat
104 declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32)
106 %z = call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %a, i32 %b)
109 ; CHECK: = add({{.*}}.l, {{.*}}.l):sat
111 declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32)
113 %z = call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %a, i32 %b)
116 ; CHECK: = add({{.*}}.l, {{.*}}.h):sat
146 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
148 %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
[all …]
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| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| D | nvfx_fragprog.c | 208 if (insn.sat) in nvfx_fp_emit()
452 int mask, sat, unit = 0; in nvfx_fragprog_parse_instruction() local
533 sat = finst->Instruction.Saturate; in nvfx_fragprog_parse_instruction()
537 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none)); in nvfx_fragprog_parse_instruction()
542 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, neg(tmp), none, none)); in nvfx_fragprog_parse_instruction()
549 insn = arith(sat, MOV, dst, mask, src[2], none, none); in nvfx_fragprog_parse_instruction()
553 insn = arith(sat, MOV, dst, mask, src[1], none, none); in nvfx_fragprog_parse_instruction()
558 nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none)); in nvfx_fragprog_parse_instruction()
563 …nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W… in nvfx_fragprog_parse_instruction()
565 … nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none)); in nvfx_fragprog_parse_instruction()
[all …]
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| D | nvfx_vertprog.c | 316 if(insn.sat) { in nvfx_vp_emit()
469 bool sat = false; in nvfx_vertprog_parse_instruction() local
545 sat = true; in nvfx_vertprog_parse_instruction()
553 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1])); in nvfx_vertprog_parse_instruction()
561 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none)); in nvfx_vertprog_parse_instruction()
568 insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none); in nvfx_vertprog_parse_instruction()
572 insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none); in nvfx_vertprog_parse_instruction()
577 nvfx_vp_emit(vpc, arith(sat, SCA, COS, dst, mask, none, none, src[0])); in nvfx_vertprog_parse_instruction()
582 …nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, swz(tmp, X, X, X, X), none, swz(tmp, Y, Y, Y, Y)… in nvfx_vertprog_parse_instruction()
585 nvfx_vp_emit(vpc, arith(sat, VEC, DP3, dst, mask, src[0], src[1], none)); in nvfx_vertprog_parse_instruction()
[all …]
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | usr-ovf-dep.ll | 5 ; Check that the two ":sat" instructions are in the same packet.
8 ; CHECK: :sat
9 ; CHECK-NEXT: :sat
17 %0 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rs, i32 %Ru)
18 %1 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rt, i32 %Ru)
24 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #1
|
| D | alu64.ll | 180 ; CHECK: = add(r1:0, r3:2):sat
260 ; CHECK: = add(r0.l, r1.l):sat
263 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt)
268 ; CHECK: = add(r0.l, r1.h):sat
271 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt)
308 ; CHECK: = add(r0.l, r1.l):sat:<<16
311 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
316 ; CHECK: = add(r0.l, r1.h):sat:<<16
319 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
324 ; CHECK: = add(r0.h, r1.l):sat:<<16
[all …]
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| /external/robolectric/v1/src/main/java/com/xtremelabs/robolectric/shadows/ |
| D | ShadowColorMatrix.java | 38 public void setSaturation(float sat) { in setSaturation() argument
42 final float invSat = 1 - sat; in setSaturation()
47 m[0] = R + sat; in setSaturation()
52 m[6] = G + sat; in setSaturation()
57 m[12] = B + sat; in setSaturation()
|
| /external/skia/src/effects/ |
| D | SkColorMatrix.cpp | 148 void SkColorMatrix::setSaturation(SkScalar sat) { in setSaturation() argument
151 const SkScalar R = kHueR * (1 - sat); in setSaturation()
152 const SkScalar G = kHueG * (1 - sat); in setSaturation()
153 const SkScalar B = kHueB * (1 - sat); in setSaturation()
155 setrow(fMat + 0, R + sat, G, B); in setSaturation()
156 setrow(fMat + 5, R, G + sat, B); in setSaturation()
157 setrow(fMat + 10, R, G, B + sat); in setSaturation()
|
| /external/autotest/client/site_tests/hardware_SAT/ |
| D | hardware_SAT.py | 124 sat = utils.run('stressapptest' + args)
125 logging.debug(sat.stdout)
126 if not re.search('Status: PASS', sat.stdout):
127 raise error.TestFail(sat.stdout)
|
| /external/autotest/client/site_tests/hardware_GobiGPS/ |
| D | hardware_GobiGPS.py | 46 sat = fields[0]
48 sats_seen[sat] = True
49 sats_signal[sat] = fields[3]
51 sats_seen[sat] = True
|
| /external/clang/test/CodeGen/ |
| D | struct-matching-constraint.c | 6 void b(uint16x8_t sat, uint16x8_t luma) in b() argument
10 :"=w"(luma), "=w"(sat) in b()
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | bit.ll | 12 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)
17 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind
31 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7)
36 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind
50 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7)
55 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind
69 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7)
74 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind
88 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7)
93 declare <16 x i8> @llvm.mips.sat.u.b(<16 x i8>, i32) nounwind
[all …]
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| /external/icu/icu4c/source/data/translit/ |
| D | sat_am.txt | 8 # TODO: Add other scripts (eg. sat-Beng) once we can transcribe them to IPA.
9 # Do this in a separate rule for "sat-sat_FONIPA", so it can be reused.
|
| D | sat_ar.txt | 8 # TODO: Add other scripts (eg. sat-Beng) once we can transcribe them to IPA.
9 # Do this in a separate rule for "sat-sat_FONIPA", so it can be reused.
|