| /external/llvm/test/CodeGen/MIR/AMDGPU/ |
| D | target-index-operands.mir | 55 …gpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
56 …gpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
57 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
58 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
60 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
61 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
62 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
63 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
64 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
65 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
[all …]
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| D | invalid-target-index-operand.mir | 47 %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
48 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
49 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
52 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
53 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
54 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
55 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
56 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
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| D | expected-target-index-name.mir | 47 %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
48 … %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
49 %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
52 %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
53 %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
54 %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
55 %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
56 %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
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| /external/libxml2/result/schemas/ |
| D | scc-no-xmlns_0_0.err | 1 ./test/schemas/scc-no-xmlns_0.xsd:7: element attribute: Schemas parser error : Element '{http://www…
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| D | scc-no-xsi_0_0.err | 1 ./test/schemas/scc-no-xsi_0.xsd:7: element attribute: Schemas parser error : Element '{http://www.w…
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| /external/llvm/test/Transforms/Inline/ |
| D | gvn-inline-iteration.ll | 1 ; RUN: opt -basicaa -inline -gvn -S -max-cg-scc-iterations=1 < %s | FileCheck %s
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| D | crash2.ll | 1 ; RUN: opt -inline -sroa -max-cg-scc-iterations=1 -disable-output < %s
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| /external/swiftshader/third_party/LLVM/test/Transforms/Inline/ |
| D | gvn-inline-iteration.ll | 1 ; RUN: opt -basicaa -inline -gvn %s -S -max-cg-scc-iterations=1 | FileCheck %s
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| D | crash2.ll | 1 ; RUN: opt -inline -scalarrepl -max-cg-scc-iterations=1 %s -disable-output
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | indirect-addressing-undef.mir | 111 # CHECK: %m0 = S_ADD_I32 %m0, -7, implicit-def %scc
223 # CHECK: %m0 = S_ADD_I32 %m0, -7, implicit-def %scc
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| D | split-scalar-i64-add.ll | 8 ; scc instead.
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| D | uniform-cfg.ll | 401 ; the first, leaving an scc use in a different block than it was
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| /external/c-ares/ |
| D | ares_init.c | 103 static char *try_config(char *s, const char *opt, char scc);
1563 static char *try_config(char *s, const char *opt, char scc) in try_config() argument
1578 if(scc) in try_config()
1579 while (*p && (*p != '#') && (*p != scc)) in try_config()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 44 def SCC : SIReg<"scc", 253>;
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| /external/llvm/test/MC/Lanai/ |
| D | v11.s | 437 scc %r21 label
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| /external/syslinux/gpxe/src/drivers/net/e1000/ |
| D | e1000_hw.h | 1322 uint64_t scc; member
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| /external/icu/icu4c/source/data/misc/ |
| D | metadata.txt | 986 scc{
|