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Searched refs:sel1 (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dmachine-combiner.ll379 %sel1 = select i1 %cmp1, float %x2, float %t0
380 %cmp2 = fcmp olt float %x3, %sel1
381 %sel2 = select i1 %cmp2, float %x3, float %sel1
403 %sel1 = select i1 %cmp1, float %x2, float %t0
404 %cmp2 = fcmp ogt float %x3, %sel1
405 %sel2 = select i1 %cmp2, float %x3, float %sel1
427 %sel1 = select i1 %cmp1, double %x2, double %t0
428 %cmp2 = fcmp olt double %x3, %sel1
429 %sel2 = select i1 %cmp2, double %x3, double %sel1
451 %sel1 = select i1 %cmp1, double %x2, double %t0
[all …]
Dcmovcmov.ll271 %sel1 = select i1 %c2, i8 20, i8 %sel0
272 %sel2 = select i1 %c0, i8 %sel1, i8 %sel0
Davx512bw-intrinsics-fast-isel.ll192 %sel1 = load <64 x i1>, <64 x i1>* %arg1
196 %res1 = select <64 x i1> %sel1, <64 x i8> %res0, <64 x i8> %arg0
318 %sel1 = load <64 x i1>, <64 x i1>* %arg1
322 %res1 = select <64 x i1> %sel1, <64 x i8> %res0, <64 x i8> %arg0
Davx512-mask-op.ll994 %sel1 = fcmp ogt <8 x double>%in, %val1
995 %val3 = select <8 x i1> %sel1, <8 x double> %val2, <8 x double> zeroinitializer
997 %sel3 = and <8 x i1> %sel1, %sel2
1352 %sel1 = fcmp ogt <32 x float>%in, %val1
1353 %val3 = select <32 x i1> %sel1, <32 x float> %val2, <32 x float> zeroinitializer
1355 %sel3 = or <32 x i1> %sel1, %sel2
/external/llvm/test/Transforms/InstCombine/
Dselect-select.ll27 ; CHECK: %[[sel1:.*]] = select i1 %bool, <2 x i32> %[[sel0]], <2 x i32> %V
28 ; CHECK: ret <2 x i32> %[[sel1]]
30 %sel1 = select i1 %bool, <2 x i32> %sel0, <2 x i32> %V
31 ret <2 x i32> %sel1
Dsub.ll556 %sel1 = select i1 %A, i32 %C, i32 %B
557 %sub = sub i32 %sel0, %sel1
567 %sel1 = select i1 %A, i32 %B, i32 %C
568 %sub = sub i32 %sel0, %sel1
Dadd2.ll401 %sel1 = select i1 %A, i32 %B, i32 2
402 %add = add i32 %sel0, %sel1
Dselect.ll846 %sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2
848 store <4 x i32> %sel1, <4 x i32>* %ptr1
869 %sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2
871 store <4 x i32> %sel1, <4 x i32>* %ptr1, align 16
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll162 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
165 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
181 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
184 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
200 %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0
203 store volatile <4 x i32> %sel1, <4 x i32> addrspace(1)* %out1, align 4
218 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
221 store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
Dsext-in-reg.ll375 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
376 %xor = xor i8 %sel0, %sel1
387 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
388 %xor = xor i8 %sel0, %sel1
/external/llvm/test/CodeGen/Hexagon/
Dgp-rel.ll31 %sel1 = select i1 %cmp2, i32 %2, i32 %1
32 ret i32 %sel1
/external/llvm/test/Analysis/Lint/
Dcppeh-catch-intrinsics-clean.ll72 %sel1 = extractvalue { i8*, i32 } %l1.0, 1
74 %matchesl1 = icmp eq i32 %sel1, %l1.1
79 %sel2 = phi i32 [%sel, %lpad], [%sel1, %lpad1]
/external/clang/test/SemaObjC/
Darc-peformselector.m15 SEL sel1; field
28 …return [self performSelector : sel1]; // expected-warning {{performSelector may cause a leak becau…
/external/llvm/test/CodeGen/AArch64/
Ddag-combine-select.ll17 %sel1 = select i1 %cmp2, i32 %v1, i32 %sel0
18 ret i32 %sel1
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-load.ll33 %sel1 = and i1 %cmp23, %cmp25
34 br i1 %sel1, label %while.body, label %while.end422
/external/llvm/test/CodeGen/SystemZ/
Dasm-18.ll544 %sel1 = select i1 %cmp1, i32 100, i32 200
547 "=h,r,r"(i32 %sel1, i32 %sel2)
684 %sel1 = select i1 %cmp1, i32 0, i32 1
685 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
701 %sel1 = select i1 %cmp1, i32 0, i32 1
702 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
719 %sel1 = select i1 %cmp1, i32 0, i32 1
720 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
739 %sel1 = select i1 %cmp1, i32 0, i32 1
740 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
Dfp-cmp-02.ll147 %sel1 = select i1 %cmp1, double %sel0, double 1.0
148 %sel2 = select i1 %cmp2, double %sel1, double 2.0
Dfp-cmp-01.ll138 %sel1 = select i1 %cmp1, float %sel0, float 1.0
139 %sel2 = select i1 %cmp2, float %sel1, float 2.0
Dint-cmp-05.ll281 %sel1 = select i1 %cmp1, i64 %sel0, i64 1
282 %sel2 = select i1 %cmp2, i64 %sel1, i64 2
Dint-cmp-06.ll331 %sel1 = select i1 %cmp1, i64 %sel0, i64 1
332 %sel2 = select i1 %cmp2, i64 %sel1, i64 2
/external/python/cpython2/Demo/tix/
Dtixwidgets.py380 sel1 = Tix.Select(w, label='Mere Mortals', allowzero=1, radio=1,
389 sel1.add('eat', text='Eat')
390 sel1.add('work', text='Work')
391 sel1.add('play', text='Play')
392 sel1.add('party', text='Party')
393 sel1.add('sleep', text='Sleep')
401 sel1.pack(side=Tix.LEFT, padx=5, pady=3, fill=Tix.X)
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dselect.ll6 define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
/external/kernel-headers/original/uapi/linux/
Dkvm.h355 __u8 sel1; member
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_sample.c1593 LLVMValueRef sel1, in lp_build_select3() argument
1600 return lp_build_select(sel_bld, sel1, val2, tmp); in lp_build_select3()