| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 249 MI->getOperand(0).setSubReg(KilledProdSubReg); in processBlock()
250 MI->getOperand(1).setSubReg(KilledProdSubReg); in processBlock()
251 MI->getOperand(3).setSubReg(AddSubReg); in processBlock()
265 MI->getOperand(2).setSubReg(AddSubReg); in processBlock()
270 MI->getOperand(2).setSubReg(OtherProdSubReg); in processBlock()
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| D | PPCVSXCopy.cpp | 148 SrcMO.setSubReg(IsVRReg(DstMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
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| D | PPCInstrInfo.cpp | 390 MI.getOperand(0).setSubReg(SubReg2); in commuteInstructionImpl()
394 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
395 MI.getOperand(1).setSubReg(SubReg2); in commuteInstructionImpl()
1804 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second); in optimizeCompareInstr()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 306 Dst.setSubReg(Src.getSubReg()); in ChangeOpInto()
321 Dst.setSubReg(Src.getSubReg()); in ChangeOpInto()
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| D | RDFCopy.cpp | 218 Op.setSubReg(SR.Sub); in run()
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| D | HexagonBitSimplify.cpp | 336 I->setSubReg(NewSR); in replaceRegWithSub()
354 I->setSubReg(NewSR); in replaceSubWithSub()
1831 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
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| D | HexagonExpandCondsets.cpp | 933 Op.setSubReg(RN.Sub); in renameInRange()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 545 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
808 MOSrc.setSubReg(NewSubReg); in RewriteCurrentSource()
946 NewCopy->getOperand(0).setSubReg(Def.SubReg); in RewriteSource()
1010 MO.setSubReg(NewSubReg); in RewriteCurrentSource()
1140 MO.setSubReg(NewSubReg); in RewriteCurrentSource()
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| D | TwoAddressInstructionPass.cpp | 1431 SrcMO.setSubReg(0); in collectTiedOperands()
1549 MO.setSubReg(0); in processTiedPairs()
1566 MO.setSubReg(0); in processTiedPairs()
1698 mi->getOperand(0).setSubReg(SubIdx); in runOnMachineFunction()
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| D | TargetInstrInfo.cpp | 180 CommutedMI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
184 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
185 CommutedMI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
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| D | VirtRegMap.cpp | 443 MO.setSubReg(0); in rewrite()
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| D | LiveDebugVariables.cpp | 813 MO.setSubReg(locations[OldLocNo].getSubReg()); in splitLocation()
935 Loc.setSubReg(0); in rewriteLocations()
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| D | TailDuplicator.cpp | 386 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(), in duplicateInstruction()
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| D | MachineInstr.cpp | 84 setSubReg(SubIdx); in substVirtReg()
93 setSubReg(0); in substPhysReg()
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| D | RegAllocFast.cpp | 695 MO.setSubReg(0); in setPhysReg()
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| D | RegisterCoalescer.cpp | 977 DefMO.setSubReg(0); in reMaterializeTrivialDef()
1037 NewMI.getOperand(0).setSubReg(NewIdx); in reMaterializeTrivialDef()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 347 void setSubReg(unsigned subReg) { in setSubReg() function
628 Op.setSubReg(SubReg);
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | VirtRegRewriter.cpp | 958 MI->getOperand(NewOp.Operand).setSubReg(0); in GetRegForReload()
2072 MI.getOperand(i).setSubReg(0); in ProcessUses()
2158 MI.getOperand(i).setSubReg(0); in ProcessUses()
2184 MI.getOperand(i).setSubReg(0); in ProcessUses()
2242 MI.getOperand(i).setSubReg(0); in ProcessUses()
2586 MI.getOperand(i).setSubReg(0); in RewriteMBB()
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| D | VirtRegMap.cpp | 310 MO.setSubReg(0); in rewrite()
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| D | LiveDebugVariables.cpp | 776 MO.setSubReg(locations[OldLocNo].getSubReg()); in splitLocation()
898 Loc.setSubReg(0); in rewriteLocations()
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| D | MachineInstr.cpp | 124 setSubReg(SubIdx); in substVirtReg()
133 setSubReg(0); in substPhysReg()
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| D | RegAllocFast.cpp | 636 MO.setSubReg(0); in setPhysReg()
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| D | TwoAddressInstructionPass.cpp | 1260 mi->getOperand(0).setSubReg(SubIdx); in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineOperand.h | 295 void setSubReg(unsigned subReg) { in setSubReg() function
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1015 Src1.setSubReg(SubReg); in commuteInstructionImpl()
1268 Src0->setSubReg(Src1SubReg); in FoldImmediate()
2116 Src0.setSubReg(Src1.getSubReg()); in legalizeOperandsVOP2()
2121 Src1.setSubReg(Src0SubReg); in legalizeOperandsVOP2()
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