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Searched refs:shsub8 (Results 1 – 20 of 20) sorted by relevance

/external/valgrind/none/tests/arm/
Dv6media.stdout.exp2551 shsub8 r0, r1, r2 :: rd 0x00f8fffe rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 g…
2552 shsub8 r0, r1, r2 :: rd 0x00070002 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 g…
2553 shsub8 r0, r1, r2 :: rd 0x00020007 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 g…
2554 shsub8 r0, r1, r2 :: rd 0xfffe00f8 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 g…
2555 shsub8 r0, r1, r2 :: rd 0x3fff3fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 g…
2556 shsub8 r0, r1, r2 :: rd 0x7fffc0ff rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 g…
2557 shsub8 r0, r1, r2 :: rd 0xc000c000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 g…
2558 shsub8 r0, r1, r2 :: rd 0xc000c000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 g…
2559 shsub8 r0, r1, r2 :: rd 0xf5fb3d37 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 g…
2560 shsub8 r0, r1, r2 :: rd 0x353f19cc rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 g…
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc65 M(shsub8) \
Dtest-assembler-cond-rd-rn-rm-a32.cc66 M(shsub8) \
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s1571 shsub8 r4, r8, r2
1576 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6]
Dbasic-thumb2-instructions.s1813 shsub8 r4, r8, r2
1819 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xc8,0xfa,0x22,0xf4]
/external/vixl/src/aarch32/
Dassembler-aarch32.h2969 void shsub8(Condition cond, Register rd, Register rn, Register rm);
2970 void shsub8(Register rd, Register rn, Register rm) { shsub8(al, rd, rn, rm); } in shsub8() function
Ddisasm-aarch32.h957 void shsub8(Condition cond, Register rd, Register rn, Register rm);
Dassembler-aarch32.cc8972 void Assembler::shsub8(Condition cond, Register rd, Register rn, Register rm) { in shsub8() function in vixl::aarch32::Assembler
8989 Delegate(kShsub8, &Assembler::shsub8, cond, rd, rn, rm); in shsub8()
Ddisasm-aarch32.cc2537 void Disassembler::shsub8(Condition cond, in shsub8() function in vixl::aarch32::Disassembler
21271 shsub8(CurrentCond(), in DecodeT32()
63182 shsub8(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
Dmacro-assembler-aarch32.h3590 shsub8(cond, rd, rn, rm); in Shsub8()
/external/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s2248 shsub8 r4, r8, r2
2254 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xc8,0xfa,0x22,0xf4]
Dbasic-arm-instructions.s2353 shsub8 r4, r8, r2
2358 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1400 # CHECK: shsub8 r4, r8, r2
Dthumb2.txt1593 # CHECK: shsub8 r4, r8, r2
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1732 # CHECK: shsub8 r4, r8, r2
Dbasic-arm-instructions.txt1561 # CHECK: shsub8 r4, r8, r2
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td1975 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
DARMInstrInfo.td3208 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2180 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
DARMInstrInfo.td3609 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;