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Searched refs:simm13 (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td389 // inc simm13, rd -> add rd, simm13, rd
390 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
395 // inccc simm13, rd -> addcc rd, simm13, rd
396 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
401 // dec simm13, rd -> sub rd, simm13, rd
402 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
407 // deccc simm13, rd -> subcc rd, simm13, rd
408 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
412 def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
416 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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DSparcInstr64Bit.td64 // The ALU instructions want their simm13 operands as i32 immediates.
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
99 // (sllx simm13, n)
103 // (xor (sllx sethi), simm13)
104 // (sllx (xor sethi, simm13))
113 // (or (sllx sethi), (or sethi, simm13))
114 // (xnor (sllx sethi), (or sethi, simm13))
120 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
180 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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DSparcInstrInfo.td76 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
297 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
298 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
299 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
312 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
420 let rd = 0, rs1 = 1, simm13 = 3 in
657 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
658 "andn $rs1, $simm13, $rd", []>;
667 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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DSparcInstrFormats.td147 bits<13> simm13;
153 let Inst{12-0} = simm13;
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp387 unsigned simm13 = 0; in DecodeMem() local
389 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeMem()
407 MI.addOperand(MCOperand::createImm(simm13)); in DecodeMem()
542 unsigned simm13 = 0; in DecodeJMPL() local
544 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeJMPL()
560 MI.addOperand(MCOperand::createImm(simm13)); in DecodeJMPL()
575 unsigned simm13 = 0; in DecodeReturn() local
577 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeReturn()
588 MI.addOperand(MCOperand::createImm(simm13)); in DecodeReturn()
606 unsigned simm13 = 0; in DecodeSWAP() local
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcInstrFormats.td93 bits<13> simm13;
99 let Inst{12-0} = simm13;
DSparcInstrInfo.td48 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
189 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
230 let rd = 0, rs1 = 1, simm13 = 3 in
301 "jmp %o7+$val", [(retflag simm13:$val)]>;
785 def : Pat<(i32 simm13:$val),
794 def : Pat<(subc IntRegs:$b, simm13:$val),
/external/valgrind/VEX/priv/
Dhost_arm_defs.h140 Int simm13; /* -4095 .. +4095 */ member
151 extern ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 );
Dhost_arm_defs.c205 ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ) { in ARMAMode1_RI() argument
209 am->ARMam1.RI.simm13 = simm13; in ARMAMode1_RI()
210 vassert(-4095 <= simm13 && simm13 <= 4095); in ARMAMode1_RI()
226 vex_printf("%d(", am->ARMam1.RI.simm13); in ppARMAMode1()
3047 if (am->ARMam1.RI.simm13 < 0) { in do_load_or_store32()
3049 simm12 = -am->ARMam1.RI.simm13; in do_load_or_store32()
3052 simm12 = am->ARMam1.RI.simm13; in do_load_or_store32()
3204 if (am->ARMam1.RI.simm13 < 0) { in emit_ARMInstr()
3206 simm12 = -am->ARMam1.RI.simm13; in emit_ARMInstr()
3209 simm12 = am->ARMam1.RI.simm13; in emit_ARMInstr()
Dhost_arm_isel.c886 && am->ARMam1.RI.simm13 >= -4095 in sane_AMode1()
887 && am->ARMam1.RI.simm13 <= 4095 ); in sane_AMode1()
/external/llvm/docs/
DWritingAnLLVMBackend.rst814 [(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;