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/external/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s11 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
18 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
21 # CHECK-EL: sllv $2, $2, $3 # encoding: [0x43,0x00,0x10,0x10]
31 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
38 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
41 # CHECK-EB: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
48 sllv $2, $3, $5
Drotations32.s12 # CHECK-32: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
19 # CHECK-32: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
52 # CHECK-32: sllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x04]
58 # CHECK-32: sllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x04]
Drotations64.s12 # CHECK-64: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
19 # CHECK-64: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
52 # CHECK-64: sllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x04]
58 # CHECK-64: sllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x04]
Dmips-alu-instructions.s22 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
53 sllv $2, $3, $5
Dmips64-alu-instructions.s20 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
48 sllv $2, $3, $5
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dshl.ll47 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
52 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
56 ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
68 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
73 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
77 ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
88 ; ALL: sllv $2, $4, $5
98 ; M2: sllv $[[T0:[0-9]+]], $5, $7
102 ; M2: sllv $[[T2:[0-9]+]], $4, $7
115 ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
[all …]
Dlshr.ll89 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
102 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
113 ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
128 ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
139 ; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
Dashr.ll91 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
104 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
122 ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
134 ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
151 ; MMR6: sllv $[[T9:[0-9]+]], $[[T7]], $[[T8]]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll84 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
86 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
115 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
117 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
146 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
148 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
178 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
180 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
207 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
210 ; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-arith.ll268 ; MIPS32: sllv
269 ; MIPS32: sllv
270 ; MIPS32: sllv
271 ; MIPS32: sllv
272 ; MIPS32: sllv
273 ; MIPS32: sllv
274 ; MIPS32: sllv
275 ; MIPS32: sllv
276 ; MIPS32: sllv
277 ; MIPS32: sllv
[all …]
Dnacl-atomic-intrinsics.ll360 ; MIPS32: sllv
362 ; MIPS32: sllv
401 ; MIPS32: sllv
403 ; MIPS32: sllv
638 ; MIPS32: sllv
640 ; MIPS32: sllv
680 ; MIPS32: sllv
682 ; MIPS32: sllv
806 ; MIPS32: sllv
808 ; MIPS32: sllv
[all …]
/external/llvm/test/CodeGen/Mips/
Datomic.ll140 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
142 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
185 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
187 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
230 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
232 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
276 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
278 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
318 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
321 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
[all …]
Dsll2.ll12 ; 16: sllv ${{[0-9]+}}, ${{[0-9]+}}
/external/valgrind/none/tests/mips32/
DMIPS32int.stdout.exp-mips32-LE637 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
638 sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
639 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
640 sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
641 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
642 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
643 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
644 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
645 sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
646 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32-BE637 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
638 sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
639 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
640 sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
641 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
642 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
643 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
644 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
645 sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
646 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-BE1115 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
1116 sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1117 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1118 sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1119 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1120 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1121 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
1122 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1123 sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1124 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-LE1115 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
1116 sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1117 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1118 sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1119 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1120 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1121 sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
1122 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1123 sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1124 sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
/external/llvm/test/MC/Mips/mips1/
Dvalid.s92 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
93 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips6415873 sllv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
15874 sllv $s0, $s1, $s2 :: rd 0x257ad54, rs 0x12bd6aa, rt 0xa2a6ec661ba84121
15875 sllv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
15876 sllv $s0, $s1, $s2 :: rd 0xffffffff95589800, rs 0x7e876382d2ab13, rt 0x614d9b445f12236b
15877 sllv $t0, $t1, $t2 :: rd 0xffffffffb8000000, rs 0x9823b6e, rt 0xffffffffb8757bda
15878 sllv $s0, $s1, $s2 :: rd 0x1e600000, rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75
15879 sllv $t0, $t1, $t2 :: rd 0x64db2000, rs 0xd4326d9, rt 0xffffffffbcb4666d
15880 sllv $s0, $s1, $s2 :: rd 0xffffffffb5a97ec0, rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666
15881 sllv $t0, $t1, $t2 :: rd 0x476dc00, rs 0x130476dc, rt 0xffffffffa2f33668
15882 sllv $s0, $s1, $s2 :: rd 0xffffffff81000000, rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17
[all …]
/external/llvm/test/MC/Mips/mips2/
Dvalid.s118 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
119 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
/external/llvm/test/MC/Mips/mips32/
Dvalid.s148 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
149 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s183 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
184 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s183 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
184 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s184 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
185 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s183 … sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
184 … sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]

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