| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-smaxv.ll | 5 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
9 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
16 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
20 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
32 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
38 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
42 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
49 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
53 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
60 ; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
[all …]
|
| D | arm64-neon-across.ll | 47 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
49 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
51 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
57 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
59 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
167 ; CHECK: smaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
169 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
170 %0 = trunc i32 %smaxv.i to i8
176 ; CHECK: smaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
178 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)
[all …]
|
| D | aarch64-minmaxv.ll | 7 ; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
29 ; CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
48 ; CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
64 ; CHECK-NOT: smaxv
420 ; CHECK: smaxv {{h[0-9]+}}, [[V0]]
445 ; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-across.s | 33 smaxv b0, v1.8b
34 smaxv b0, v1.16b
35 smaxv h0, v1.4h
36 smaxv h0, v1.8h
37 smaxv s0, v1.4s
|
| D | neon-diagnostics.s | 3773 smaxv s0, v1.2s
3795 smaxv d0, v1.2d define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1455 __ smaxv(b4, v5.V16B()); in GenerateTestSequenceNEON() local
1456 __ smaxv(b23, v0.V8B()); in GenerateTestSequenceNEON() local
1457 __ smaxv(h6, v0.V4H()); in GenerateTestSequenceNEON() local
1458 __ smaxv(h24, v8.V8H()); in GenerateTestSequenceNEON() local
1459 __ smaxv(s3, v16.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4406 DEFINE_TEST_NEON_ACROSS(smaxv, Basic)
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 1221 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
1222 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
1223 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
1224 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
1225 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
|
| D | log-disasm-colour | 1221 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
1222 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
1223 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
1224 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
1225 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
|
| D | log-all | 3265 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
3267 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
3269 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
3271 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
3273 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2092 void smaxv(const VRegister& vd, const VRegister& vn);
|
| D | simulator-aarch64.h | 2270 LogicVRegister smaxv(VectorFormat vform,
|
| D | macro-assembler-aarch64.h | 2309 V(smaxv, Smaxv) \
|
| D | simulator-aarch64.cc | 3715 smaxv(vf, rd, rn); in VisitNEONAcrossLanes()
|
| D | logic-aarch64.cc | 1506 LogicVRegister Simulator::smaxv(VectorFormat vform, in smaxv() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 3484 V(smaxv, NEON_SMAXV, true) \
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3164 void smaxv(const VRegister& vd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4126 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 262 aarch64_neon_smaxv, // llvm.aarch64.neon.smaxv
6320 "llvm.aarch64.neon.smaxv",
14260 1, // llvm.aarch64.neon.smaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 254 aarch64_neon_smaxv, // llvm.aarch64.neon.smaxv
6278 "llvm.aarch64.neon.smaxv",
14163 1, // llvm.aarch64.neon.smaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 262 aarch64_neon_smaxv, // llvm.aarch64.neon.smaxv
6320 "llvm.aarch64.neon.smaxv",
14260 1, // llvm.aarch64.neon.smaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 262 aarch64_neon_smaxv, // llvm.aarch64.neon.smaxv
6320 "llvm.aarch64.neon.smaxv",
14260 1, // llvm.aarch64.neon.smaxv
|