| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-sminv.ll | 5 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
9 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
16 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
20 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
32 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
38 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
42 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
49 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
53 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
60 ; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
[all …]
|
| D | arm64-neon-across.ll | 27 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
29 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
31 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
37 declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
39 declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
255 ; CHECK: sminv b{{[0-9]+}}, {{v[0-9]+}}.8b
257 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a)
258 %0 = trunc i32 %sminv.i to i8
264 ; CHECK: sminv h{{[0-9]+}}, {{v[0-9]+}}.4h
266 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a)
[all …]
|
| D | aarch64-minmaxv.ll | 149 ; CHECK: sminv {{b[0-9]+}}, {{v[0-9]+}}.16b
171 ; CHECK: sminv {{h[0-9]+}}, {{v[0-9]+}}.8h
190 ; CHECK: sminv {{s[0-9]+}}, {{v[0-9]+}}.4s
206 ; CHECK-NOT: sminv
468 ; CHECK: sminv {{h[0-9]+}}, [[V0]]
493 ; CHECK-NEXT: sminv {{s[0-9]+}}, [[V0]]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-across.s | 45 sminv b0, v1.8b
46 sminv b0, v1.16b
47 sminv h0, v1.4h
48 sminv h0, v1.8h
49 sminv s0, v1.4s
|
| D | neon-diagnostics.s | 3774 sminv s0, v1.2s
3796 sminv d0, v1.2d define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1472 __ sminv(b8, v6.V16B()); in GenerateTestSequenceNEON() local
1473 __ sminv(b6, v18.V8B()); in GenerateTestSequenceNEON() local
1474 __ sminv(h20, v1.V4H()); in GenerateTestSequenceNEON() local
1475 __ sminv(h7, v17.V8H()); in GenerateTestSequenceNEON() local
1476 __ sminv(s21, v4.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4407 DEFINE_TEST_NEON_ACROSS(sminv, Basic)
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 1238 0x~~~~~~~~~~~~~~~~ 4e31a8c8 sminv b8, v6.16b
1239 0x~~~~~~~~~~~~~~~~ 0e31aa46 sminv b6, v18.8b
1240 0x~~~~~~~~~~~~~~~~ 0e71a834 sminv h20, v1.4h
1241 0x~~~~~~~~~~~~~~~~ 4e71aa27 sminv h7, v17.8h
1242 0x~~~~~~~~~~~~~~~~ 4eb1a895 sminv s21, v4.4s
|
| D | log-disasm-colour | 1238 0x~~~~~~~~~~~~~~~~ 4e31a8c8 sminv b8, v6.16b
1239 0x~~~~~~~~~~~~~~~~ 0e31aa46 sminv b6, v18.8b
1240 0x~~~~~~~~~~~~~~~~ 0e71a834 sminv h20, v1.4h
1241 0x~~~~~~~~~~~~~~~~ 4e71aa27 sminv h7, v17.8h
1242 0x~~~~~~~~~~~~~~~~ 4eb1a895 sminv s21, v4.4s
|
| D | log-all | 3299 0x~~~~~~~~~~~~~~~~ 4e31a8c8 sminv b8, v6.16b
3301 0x~~~~~~~~~~~~~~~~ 0e31aa46 sminv b6, v18.8b
3303 0x~~~~~~~~~~~~~~~~ 0e71a834 sminv h20, v1.4h
3305 0x~~~~~~~~~~~~~~~~ 4e71aa27 sminv h7, v17.8h
3307 0x~~~~~~~~~~~~~~~~ 4eb1a895 sminv s21, v4.4s
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2101 void sminv(const VRegister& vd, const VRegister& vn);
|
| D | simulator-aarch64.h | 2273 LogicVRegister sminv(VectorFormat vform,
|
| D | macro-assembler-aarch64.h | 2310 V(sminv, Sminv) \
|
| D | simulator-aarch64.cc | 3718 sminv(vf, rd, rn); in VisitNEONAcrossLanes()
|
| D | logic-aarch64.cc | 1514 LogicVRegister Simulator::sminv(VectorFormat vform, in sminv() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 3485 V(sminv, NEON_SMINV, true) \
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3190 void sminv(const VRegister& vd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4127 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 265 aarch64_neon_sminv, // llvm.aarch64.neon.sminv
6323 "llvm.aarch64.neon.sminv",
14263 1, // llvm.aarch64.neon.sminv
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 257 aarch64_neon_sminv, // llvm.aarch64.neon.sminv
6281 "llvm.aarch64.neon.sminv",
14166 1, // llvm.aarch64.neon.sminv
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 265 aarch64_neon_sminv, // llvm.aarch64.neon.sminv
6323 "llvm.aarch64.neon.sminv",
14263 1, // llvm.aarch64.neon.sminv
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 265 aarch64_neon_sminv, // llvm.aarch64.neon.sminv
6323 "llvm.aarch64.neon.sminv",
14263 1, // llvm.aarch64.neon.sminv
|