| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ShrinkWrapping.cpp | 948 CSRegSet spilled = BI->second; in verifySpillRestorePlacement() local
951 if (spilled.empty()) in verifySpillRestorePlacement()
955 << stringifyCSRegSet(spilled) in verifySpillRestorePlacement()
959 if (CSRRestore[MBB].intersects(spilled)) { in verifySpillRestorePlacement()
960 restored |= (CSRRestore[MBB] & spilled); in verifySpillRestorePlacement()
973 if (CSRSave[SBB].intersects(spilled) && in verifySpillRestorePlacement()
974 !restored.contains(CSRSave[SBB] & spilled)) in verifySpillRestorePlacement()
978 if (CSRRestore[SBB].intersects(spilled)) in verifySpillRestorePlacement()
979 restored |= (CSRRestore[SBB] & spilled); in verifySpillRestorePlacement()
984 if (restored != spilled) { in verifySpillRestorePlacement()
[all …]
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| D | RegAllocPBQP.cpp | 146 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
491 void RegAllocPBQP::addStackInterval(const LiveInterval *spilled, in addStackInterval() argument
493 int stackSlot = vrm->getStackSlot(spilled->reg); in addStackInterval()
499 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg); in addStackInterval()
510 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); in addStackInterval()
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| /external/r8/src/main/java/com/android/tools/r8/ir/regalloc/ |
| D | LinearScanRegisterAllocator.java | 1482 private void splitRangesForSpilledArgument(LiveIntervals spilled) { in splitRangesForSpilledArgument() argument
1483 assert spilled.isSpilled(); in splitRangesForSpilledArgument()
1484 assert spilled.isArgumentInterval(); in splitRangesForSpilledArgument()
1488 if (!spilled.getUses().isEmpty()) { in splitRangesForSpilledArgument()
1489 LiveIntervals split = spilled.splitBefore(spilled.getUses().first().getPosition()); in splitRangesForSpilledArgument()
1494 private void splitRangesForSpilledInterval(LiveIntervals spilled, int registerNumber) { in splitRangesForSpilledInterval() argument
1497 assert spilled.isSpilled(); in splitRangesForSpilledInterval()
1498 assert !spilled.getValue().isConstant(); in splitRangesForSpilledInterval()
1499 assert !spilled.isLinked() || spilled.isArgumentInterval(); in splitRangesForSpilledInterval()
1500 if (spilled.isArgumentInterval()) { in splitRangesForSpilledInterval()
[all …]
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| D | LiveIntervals.java | 30 private boolean spilled = false; field in LiveIntervals
80 spilled = value; in setSpilled()
84 return spilled; in isSpilled()
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| /external/llvm/test/CodeGen/X86/ |
| D | i386-tlscall-fastregalloc.ll | 14 ; C is spilled because of the scheduling of the instructions,
15 ; but a smarter regalloc wouldn't have spilled it.
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| D | win32-spill-xmm.ll | 3 ; Check proper alignment of spilled vector
20 ; Check that proper alignment of spilled vector does not affect vargs
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| D | 2003-08-03-CallArgLiveRanges.ll | 9 ; CHECK-NOT: spilled
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| D | reghinting.ll | 5 ;; Check that they are spilled early enough that not copies are needed for the
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| D | 2010-06-15-FastAllocEarlyCLobber.ll | 14 ; The earlyclobber register EC0 should not be spilled before the inline asm.
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| D | anyregcc.ll | 306 ; Loc 0: Register (some register that will be spilled to the stack)
330 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
350 ; Loc 3: Arg2 spilled to RBP +
355 ; Loc 4: Arg3 spilled to RBP +
367 ; Make sure all regs are spilled
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| D | ssp-guard-spill.ll | 6 ; stack guard value, it may get spilled to the stack, then the for loop may
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | subreg-remat.ll | 16 ; The vector must be spilled:
41 ; The vector must not be spilled:
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| /external/llvm/test/CodeGen/ARM/ |
| D | subreg-remat.ll | 16 ; The vector must be spilled:
41 ; The vector must not be spilled:
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| D | gpr-paired-spill.ll | 15 ; one of them has to be spilled. This used to cause an abort because
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | 2003-08-03-CallArgLiveRanges.ll | 6 ; RUN: llc < %s -march=x86 -stats |& not grep spilled
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| D | reghinting.ll | 5 ;; Check that they are spilled early enough that not copies are needed for the
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| D | 2010-06-15-FastAllocEarlyCLobber.ll | 14 ; The earlyclobber register EC0 should not be spilled before the inline asm.
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| /external/llvm/test/CodeGen/AArch64/ |
| D | remat-float0.ll | 4 ; of spilled/filled.
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| D | arm64-patchpoint-scratch-regs.ll | 3 ; Test that scratch registers are spilled around patchpoints
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| D | stack-guard-remat-bitcast.ll | 9 ; Load the stack guard for the second time, just in case the previous value gets spilled.
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| D | arm64-anyregcc.ll | 301 ; Loc 0: Register (some register that will be spilled to the stack)
325 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
345 ; Loc 3: Arg2 spilled to FP -96
350 ; Loc 4: Arg3 spilled to FP - 88
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| /external/v8/src/compiler/ |
| D | register-allocator.cc | 144 new (curr) LiveRangeBound(i, i->spilled()); in Initialize()
450 DCHECK(!HasRegisterAssigned() && !spilled()); in set_assigned_register()
456 DCHECK(HasRegisterAssigned() && !spilled()); in UnsetAssignedRegister()
462 DCHECK(!spilled()); in Spill()
556 DCHECK(!spilled()); in GetAssignedOperand()
560 DCHECK(spilled()); in GetAssignedOperand()
1055 temp->set_spilled(first->spilled()); in Merge()
1056 if (!temp->spilled()) in Merge()
2713 DCHECK(!range->spilled()); in Spill()
2760 if (!to_add->spilled()) { in AllocateRegisters()
[all …]
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| D | live-range-separator.cc | 147 if (child->spilled() || in MarkRangesSpilledInDeferredBlocks()
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| /external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/ |
| D | call.ll | 26 ; vararg call: ensure that all caller-saved registers are spilled to the
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc64-anyregcc.ll | 328 ; Loc 0: Register (some register that will be spilled to the stack)
353 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
373 ; Loc 3: Arg2 spilled to FP -96
378 ; Loc 4: Arg3 spilled to FP - 88
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