| /external/mesa3d/src/gallium/drivers/r600/ |
| D | evergreen_hw_context.c | 35 uint64_t src_offset, in evergreen_dma_copy_buffer() argument
50 src_offset += rsrc->gpu_address; in evergreen_dma_copy_buffer()
53 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) { in evergreen_dma_copy_buffer()
73 radeon_emit(cs, src_offset & 0xffffffff); in evergreen_dma_copy_buffer()
75 radeon_emit(cs, (src_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
77 src_offset += csize << shift; in evergreen_dma_copy_buffer()
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| D | r600_hw_context.c | 442 struct pipe_resource *src, uint64_t src_offset, in r600_cp_dma_copy_buffer() argument
457 src_offset += r600_resource(src)->gpu_address; in r600_cp_dma_copy_buffer()
491 radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */ in r600_cp_dma_copy_buffer()
492 radeon_emit(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */ in r600_cp_dma_copy_buffer()
503 src_offset += byte_count; in r600_cp_dma_copy_buffer()
524 uint64_t src_offset, in r600_dma_copy_buffer() argument
551 radeon_emit(cs, src_offset & 0xfffffffc); in r600_dma_copy_buffer()
553 radeon_emit(cs, (src_offset >> 32UL) & 0xff); in r600_dma_copy_buffer()
555 src_offset += csize << 2; in r600_dma_copy_buffer()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_dma.c | 36 uint64_t src_offset, in si_dma_copy_buffer() argument
51 src_offset += rsrc->gpu_address; in si_dma_copy_buffer()
54 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) { in si_dma_copy_buffer()
72 radeon_emit(cs, src_offset); in si_dma_copy_buffer()
74 radeon_emit(cs, (src_offset >> 32UL) & 0xff); in si_dma_copy_buffer()
76 src_offset += count; in si_dma_copy_buffer()
297 uint64_t dst_offset, src_offset; in si_dma_copy() local
303 src_offset= rsrc->surface.level[src_level].offset; in si_dma_copy()
304 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z; in si_dma_copy()
305 src_offset += src_y * src_pitch + src_x * bpp; in si_dma_copy()
[all …]
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| D | si_cp_dma.c | 305 uint64_t dst_offset, uint64_t src_offset, unsigned size, in si_copy_buffer() argument
318 if (dst != src || dst_offset != src_offset) { in si_copy_buffer()
327 src_offset += r600_resource(src)->gpu_address; in si_copy_buffer()
343 if (src_offset % CP_DMA_ALIGNMENT) { in si_copy_buffer()
344 skipped_size = CP_DMA_ALIGNMENT - (src_offset % CP_DMA_ALIGNMENT); in si_copy_buffer()
358 main_src_offset = src_offset + skipped_size; in si_copy_buffer()
384 si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size, in si_copy_buffer()
397 if (dst_offset != src_offset) in si_copy_buffer()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_pixel_draw.c | 59 GLuint src_offset; in do_blit_drawpixels() local
107 src_offset = (GLintptr)pixels; in do_blit_drawpixels()
108 src_offset += _mesa_image_offset(2, unpack, width, height, in do_blit_drawpixels()
111 src_buffer = intel_bufferobj_buffer(brw, src, src_offset, in do_blit_drawpixels()
118 src_offset, in do_blit_drawpixels()
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| D | brw_eu_validate.c | 141 for (int src_offset = 0; src_offset < p->next_insn_offset - start_offset; in brw_validate_instructions() local
142 src_offset += sizeof(brw_inst)) { in brw_validate_instructions()
144 const brw_inst *inst = store + src_offset; in brw_validate_instructions()
179 annotation_insert_error(annotation, src_offset, error_msg.str); in brw_validate_instructions()
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| D | intel_blit.c | 260 uint32_t src_offset, src_tile_x, src_tile_y; in emit_miptree_blit() local
263 &src_offset, &src_tile_x, &src_tile_y); in emit_miptree_blit()
273 src_mt->bo, src_mt->offset + src_offset, in emit_miptree_blit()
479 uintptr_t src_offset, int32_t src_pitch, in can_fast_copy_blit() argument
510 if ((dst_offset | src_offset) & 63) in can_fast_copy_blit()
576 GLuint src_offset, in intelEmitCopyBlit() argument
623 src_buffer, src_pitch, src_offset, src_x, src_y, in intelEmitCopyBlit()
639 src_offset, src_pitch, in intelEmitCopyBlit()
697 if (!alignment_valid(brw, src_offset, src_tiling)) in intelEmitCopyBlit()
703 if (src_pitch % 4 != 0 || src_offset % cpp != 0 || in intelEmitCopyBlit()
[all …]
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| D | intel_blit.h | 36 GLuint src_offset,
86 unsigned int src_offset,
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_atom_array.c | 381 int src_offset, int format, in init_velement() argument
384 velement->src_offset = src_offset; in init_velement()
394 int src_offset, int format, in init_velement_lowered() argument
408 init_velement(&velements[idx], src_offset, in init_velement_lowered()
420 init_velement(&velements[idx], src_offset + 4 * sizeof(float), in init_velement_lowered()
426 init_velement(&velements[idx], src_offset, PIPE_FORMAT_R32G32_UINT, in init_velement_lowered()
433 init_velement(&velements[idx], src_offset, in init_velement_lowered()
499 unsigned src_offset; in setup_interleaved_attribs() local
505 src_offset = (unsigned) (array->Ptr - low_addr); in setup_interleaved_attribs()
515 init_velement_lowered(st, vp, velements, src_offset, src_format, in setup_interleaved_attribs()
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| /external/mesa3d/src/gallium/drivers/vc4/kernel/ |
| D | vc4_validate.c | 479 uint32_t src_offset = 0; in vc4_validate_bin_cl() local
481 while (src_offset < len) { in vc4_validate_bin_cl()
483 void *src_pkt = unvalidated + src_offset; in vc4_validate_bin_cl()
489 src_offset, cmd); in vc4_validate_bin_cl()
496 src_offset, cmd); in vc4_validate_bin_cl()
500 if (src_offset + info->len > len) { in vc4_validate_bin_cl()
503 src_offset, cmd, info->name, info->len, in vc4_validate_bin_cl()
504 src_offset + len); in vc4_validate_bin_cl()
515 src_offset, cmd, info->name); in vc4_validate_bin_cl()
519 src_offset += info->len; in vc4_validate_bin_cl()
[all …]
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| /external/mesa3d/src/intel/vulkan/ |
| D | genX_gpu_memcpy.c | 57 struct anv_bo *src, uint32_t src_offset, in genX()
64 assert(src_offset + size <= src->size); in genX()
68 bs = gcd_pow2_u64(bs, src_offset); in genX()
97 .BufferStartingAddress = { src, src_offset }, in genX()
104 .EndAddress = { src, src_offset + size - 1 }, in genX()
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| /external/valgrind/none/tests/s390x/ |
| D | mvcl.c | 175 uint32_t dst_offset, dst_len, src_offset, src_len; in main() local
266 for (src_offset = 0; src_offset < sizeof buf; ++src_offset) in main()
267 for (src_len = 0; src_len <= sizeof buf - src_offset; ++src_len) in main()
268 run_test(buf + dst_offset, dst_len, buf + src_offset, src_len, 'x'); in main()
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| /external/strace/ |
| D | file_ioctl.c | 46 uint64_t src_offset; member
69 uint64_t src_offset; /* in - start of extent in source */ member
146 (uint64_t) args.src_offset, in file_ioctl()
174 (uint64_t) args.src_offset, in file_ioctl()
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_blit.c | 221 GLuint src_offset, in intelEmitCopyBlit() argument
245 if (src_offset & 4095) in intelEmitCopyBlit()
270 src_buffer, src_pitch, src_offset, src_x, src_y, in intelEmitCopyBlit()
276 if (src_pitch % 4 != 0 || src_offset % cpp != 0 || in intelEmitCopyBlit()
332 src_offset); in intelEmitCopyBlit()
597 unsigned int src_offset, in intel_emit_linear_blit() argument
611 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
620 src_offset += pitch * height; in intel_emit_linear_blit()
627 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
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| D | intel_blit.h | 43 GLuint src_offset,
80 unsigned int src_offset,
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| /external/mesa3d/src/gallium/drivers/i915/ |
| D | i915_blit.c | 93 unsigned src_offset, in i915_copy_blit() argument
110 src_buffer, src_pitch, src_offset, src_x, src_y, in i915_copy_blit()
157 OUT_RELOC_FENCED(src_buffer, I915_USAGE_2D_SOURCE, src_offset); in i915_copy_blit()
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| /external/mesa3d/src/gallium/auxiliary/draw/ |
| D | draw_pt_emit.c | 86 unsigned src_offset = vinfo->attrib[i].src_index * 4 * sizeof(float); in draw_pt_emit_prepare() local
96 src_offset = 0; in draw_pt_emit_prepare()
101 src_offset = 0; in draw_pt_emit_prepare()
107 hw_key.element[i].input_offset = src_offset; in draw_pt_emit_prepare()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_meta_resolve_cs.c | 73 …nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_con… in build_resolve_compute_shader() local
74 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); in build_resolve_compute_shader()
75 src_offset->num_components = 2; in build_resolve_compute_shader()
76 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset"); in build_resolve_compute_shader()
77 nir_builder_instr_insert(&b, &src_offset->instr); in build_resolve_compute_shader()
85 nir_ssa_def *img_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa); in build_resolve_compute_shader()
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| D | radv_meta_buffer.c | 356 uint64_t src_offset, uint64_t dst_offset, in copy_buffer_shader() argument
378 .offset = src_offset, in copy_buffer_shader()
452 uint64_t src_offset, uint64_t dst_offset, in radv_copy_buffer() argument
455 if (size >= 4096 && !(size & 3) && !(src_offset & 3) && !(dst_offset & 3)) in radv_copy_buffer()
457 src_offset, dst_offset, size); in radv_copy_buffer()
461 src_va += src_offset; in radv_copy_buffer()
500 uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset; in radv_CmdCopyBuffer() local
505 src_offset, dest_offset, copy_size); in radv_CmdCopyBuffer()
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| /external/pdfium/core/fpdfapi/page/ |
| D | cpdf_image.cpp | 296 int32_t src_offset = 0; in SetImage() local
299 src_offset = row * src_pitch; in SetImage()
302 pDest[dest_offset] = (uint8_t)(src_buf[src_offset + 2] * alpha); in SetImage()
303 pDest[dest_offset + 1] = (uint8_t)(src_buf[src_offset + 1] * alpha); in SetImage()
304 pDest[dest_offset + 2] = (uint8_t)(src_buf[src_offset] * alpha); in SetImage()
306 src_offset += bpp == 24 ? 3 : 4; in SetImage()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_tex_copy.c | 84 intptr_t src_offset = rrb->draw_offset; in do_copy_texsubimage() local
92 … x, y, rrb->base.Base.Width, rrb->base.Base.Height, (uint32_t) src_offset, rrb->pitch/rrb->cpp); in do_copy_texsubimage()
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp, in do_copy_texsubimage()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_tex_copy.c | 84 intptr_t src_offset = rrb->draw_offset; in do_copy_texsubimage() local
92 … x, y, rrb->base.Base.Width, rrb->base.Base.Height, (uint32_t) src_offset, rrb->pitch/rrb->cpp); in do_copy_texsubimage()
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp, in do_copy_texsubimage()
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| /external/sfntly/cpp/src/sfntly/data/ |
| D | growable_memory_byte_array.h | 40 int32_t src_offset, in CopyTo() argument
42 return ByteArray::CopyTo(dst_offset, array, src_offset, length); in CopyTo()
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| D | memory_byte_array.h | 52 int32_t src_offset, in CopyTo() argument
54 return ByteArray::CopyTo(dst_offset, array, src_offset, length); in CopyTo()
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_tiling.c | 87 for (uint32_t src_offset = 0; src_offset < 64; src_offset += src_stride) { in vc4_load_utile() local
88 memcpy(dst, src + src_offset, src_stride); in vc4_load_utile()
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