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/external/llvm/test/CodeGen/NVPTX/
Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
Dintrinsic-old.ll11 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
13 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
19 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.y(), !range ![[BLK_IDX_XY]]
21 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
27 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]]
29 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
36 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
42 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
44 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
50 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
[all …]
Dbug22322.ll13 %0 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
14 %1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
16 %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
40 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
43 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
46 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
Dldu-reg-plus-offset.ll19 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
/external/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
Ddiverge.ll10 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
32 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
53 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
103 %laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
125 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
161 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
192 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
209 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
210 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
[all …]
/external/v8/src/arm64/
Dsimulator-arm64.cc1666 case STR_s: MemoryWrite<float>(address, sreg(srcdst)); break; in LoadStoreHelper()
1795 MemoryWrite<float>(address, sreg(rt)); in LoadStorePairHelper()
1796 MemoryWrite<float>(address2, sreg(rt2)); in LoadStorePairHelper()
2264 case FCVTAS_ws: set_wreg(dst, FPToInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2265 case FCVTAS_xs: set_xreg(dst, FPToInt64(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2268 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2269 case FCVTAU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2273 set_wreg(dst, FPToInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
2276 set_xreg(dst, FPToInt64(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
2285 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
[all …]
Dsimulator-arm64.h421 float sreg(unsigned code) const {
439 case kSRegSizeInBits: return sreg(code);
/external/llvm/docs/
DNVPTXUsage.rst196 '``llvm.nvvm.read.ptx.sreg.*``'
204 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
205 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
206 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
207 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
209 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
210 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
211 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.y()
212 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.z()
[all …]
/external/v8/src/arm/
Dsimulator-arm.h173 void set_s_register_from_float(int sreg, const float flt) { in set_s_register_from_float() argument
174 SetVFPRegister<float, 1>(sreg, flt); in set_s_register_from_float()
177 float get_float_from_s_register(int sreg) { in get_float_from_s_register() argument
178 return GetFromVFPRegister<float, 1>(sreg); in get_float_from_s_register()
181 void set_s_register_from_sinteger(int sreg, const int sint) { in set_s_register_from_sinteger() argument
182 SetVFPRegister<int, 1>(sreg, sint); in set_s_register_from_sinteger()
185 int get_sinteger_from_s_register(int sreg) { in get_sinteger_from_s_register() argument
186 return GetFromVFPRegister<int, 1>(sreg); in get_sinteger_from_s_register()
Dsimulator-arm.cc934 void Simulator::set_s_register(int sreg, unsigned int value) { in set_s_register() argument
935 DCHECK((sreg >= 0) && (sreg < num_s_registers)); in set_s_register()
936 vfp_registers_[sreg] = value; in set_s_register()
940 unsigned int Simulator::get_s_register(int sreg) const { in get_s_register()
941 DCHECK((sreg >= 0) && (sreg < num_s_registers)); in get_s_register()
942 return vfp_registers_[sreg]; in get_s_register()
2386 SRegister sreg = static_cast<SRegister>(instr->BitField(22, 22)); in DecodeType01() local
2387 set_register(rd, GetFromSpecialRegister(sreg)); in DecodeType01()
/external/vixl/test/aarch32/
Dtest-utils-aarch32.cc127 const SRegister& sreg) { in Equal32() argument
128 return Equal32(expected, core, core->GetSRegisterBits(sreg.GetCode())); in Equal32()
209 const SRegister& sreg) { in EqualFP32() argument
211 uint32_t result = core->GetSRegisterBits(sreg.GetCode()); in EqualFP32()
Dtest-utils-aarch32.h174 const SRegister& sreg);
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DMemRegion.h530 CodeTextRegion(const MemRegion *sreg, Kind k) : TypedRegion(sreg, k) {} in CodeTextRegion() argument
544 FunctionCodeRegion(const NamedDecl *fd, const MemRegion* sreg) in FunctionCodeRegion() argument
545 : CodeTextRegion(sreg, FunctionCodeRegionKind), FD(fd) { in FunctionCodeRegion()
594 AnalysisDeclContext *ac, const MemRegion* sreg) in BlockCodeRegion() argument
595 : CodeTextRegion(sreg, BlockCodeRegionKind), BD(bd), AC(ac), locTy(lTy) {} in BlockCodeRegion()
636 unsigned count, const MemRegion *sreg) in BlockDataRegion() argument
637 : TypedRegion(sreg, BlockDataRegionKind), BC(bc), LC(lc), in BlockDataRegion()
712 SymbolicRegion(const SymbolRef s, const MemRegion* sreg) in SymbolicRegion() argument
713 : SubRegion(sreg, SymbolicRegionKind), sym(s) {} in SymbolicRegion()
742 StringRegion(const StringLiteral* str, const MemRegion* sreg) in StringRegion() argument
[all …]
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td882 "llvm.nvvm.read.ptx.sreg.envreg0">,
886 "llvm.nvvm.read.ptx.sreg.envreg1">,
890 "llvm.nvvm.read.ptx.sreg.envreg2">,
894 "llvm.nvvm.read.ptx.sreg.envreg3">,
898 "llvm.nvvm.read.ptx.sreg.envreg4">,
902 "llvm.nvvm.read.ptx.sreg.envreg5">,
906 "llvm.nvvm.read.ptx.sreg.envreg6">,
910 "llvm.nvvm.read.ptx.sreg.envreg7">,
914 "llvm.nvvm.read.ptx.sreg.envreg8">,
918 "llvm.nvvm.read.ptx.sreg.envreg9">,
[all …]
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h103 inline float sreg(unsigned code) const { in sreg() function
Dtest-utils-aarch64.cc183 return EqualFP32(expected, core, core->sreg(fpreg.GetCode())); in EqualFP32()
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3112 nvvm_read_ptx_sreg_clock, // llvm.nvvm.read.ptx.sreg.clock
3113 nvvm_read_ptx_sreg_clock64, // llvm.nvvm.read.ptx.sreg.clock64
3114 nvvm_read_ptx_sreg_ctaid_w, // llvm.nvvm.read.ptx.sreg.ctaid.w
3115 nvvm_read_ptx_sreg_ctaid_x, // llvm.nvvm.read.ptx.sreg.ctaid.x
3116 nvvm_read_ptx_sreg_ctaid_y, // llvm.nvvm.read.ptx.sreg.ctaid.y
3117 nvvm_read_ptx_sreg_ctaid_z, // llvm.nvvm.read.ptx.sreg.ctaid.z
3118 nvvm_read_ptx_sreg_envreg0, // llvm.nvvm.read.ptx.sreg.envreg0
3119 nvvm_read_ptx_sreg_envreg1, // llvm.nvvm.read.ptx.sreg.envreg1
3120 nvvm_read_ptx_sreg_envreg10, // llvm.nvvm.read.ptx.sreg.envreg10
3121 nvvm_read_ptx_sreg_envreg11, // llvm.nvvm.read.ptx.sreg.envreg11
[all …]
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3106 nvvm_read_ptx_sreg_clock, // llvm.nvvm.read.ptx.sreg.clock
3107 nvvm_read_ptx_sreg_clock64, // llvm.nvvm.read.ptx.sreg.clock64
3108 nvvm_read_ptx_sreg_ctaid_w, // llvm.nvvm.read.ptx.sreg.ctaid.w
3109 nvvm_read_ptx_sreg_ctaid_x, // llvm.nvvm.read.ptx.sreg.ctaid.x
3110 nvvm_read_ptx_sreg_ctaid_y, // llvm.nvvm.read.ptx.sreg.ctaid.y
3111 nvvm_read_ptx_sreg_ctaid_z, // llvm.nvvm.read.ptx.sreg.ctaid.z
3112 nvvm_read_ptx_sreg_envreg0, // llvm.nvvm.read.ptx.sreg.envreg0
3113 nvvm_read_ptx_sreg_envreg1, // llvm.nvvm.read.ptx.sreg.envreg1
3114 nvvm_read_ptx_sreg_envreg10, // llvm.nvvm.read.ptx.sreg.envreg10
3115 nvvm_read_ptx_sreg_envreg11, // llvm.nvvm.read.ptx.sreg.envreg11
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3112 nvvm_read_ptx_sreg_clock, // llvm.nvvm.read.ptx.sreg.clock
3113 nvvm_read_ptx_sreg_clock64, // llvm.nvvm.read.ptx.sreg.clock64
3114 nvvm_read_ptx_sreg_ctaid_w, // llvm.nvvm.read.ptx.sreg.ctaid.w
3115 nvvm_read_ptx_sreg_ctaid_x, // llvm.nvvm.read.ptx.sreg.ctaid.x
3116 nvvm_read_ptx_sreg_ctaid_y, // llvm.nvvm.read.ptx.sreg.ctaid.y
3117 nvvm_read_ptx_sreg_ctaid_z, // llvm.nvvm.read.ptx.sreg.ctaid.z
3118 nvvm_read_ptx_sreg_envreg0, // llvm.nvvm.read.ptx.sreg.envreg0
3119 nvvm_read_ptx_sreg_envreg1, // llvm.nvvm.read.ptx.sreg.envreg1
3120 nvvm_read_ptx_sreg_envreg10, // llvm.nvvm.read.ptx.sreg.envreg10
3121 nvvm_read_ptx_sreg_envreg11, // llvm.nvvm.read.ptx.sreg.envreg11
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3112 nvvm_read_ptx_sreg_clock, // llvm.nvvm.read.ptx.sreg.clock
3113 nvvm_read_ptx_sreg_clock64, // llvm.nvvm.read.ptx.sreg.clock64
3114 nvvm_read_ptx_sreg_ctaid_w, // llvm.nvvm.read.ptx.sreg.ctaid.w
3115 nvvm_read_ptx_sreg_ctaid_x, // llvm.nvvm.read.ptx.sreg.ctaid.x
3116 nvvm_read_ptx_sreg_ctaid_y, // llvm.nvvm.read.ptx.sreg.ctaid.y
3117 nvvm_read_ptx_sreg_ctaid_z, // llvm.nvvm.read.ptx.sreg.ctaid.z
3118 nvvm_read_ptx_sreg_envreg0, // llvm.nvvm.read.ptx.sreg.envreg0
3119 nvvm_read_ptx_sreg_envreg1, // llvm.nvvm.read.ptx.sreg.envreg1
3120 nvvm_read_ptx_sreg_envreg10, // llvm.nvvm.read.ptx.sreg.envreg10
3121 nvvm_read_ptx_sreg_envreg11, // llvm.nvvm.read.ptx.sreg.envreg11
[all …]
/external/valgrind/VEX/priv/
Dguest_x86_toIR.c484 static Int segmentGuestRegOffset ( UInt sreg ) in segmentGuestRegOffset() argument
486 switch (sreg) { in segmentGuestRegOffset()
561 static IRExpr* getSReg ( UInt sreg ) in getSReg() argument
563 return IRExpr_Get( segmentGuestRegOffset(sreg), Ity_I16 ); in getSReg()
566 static void putSReg ( UInt sreg, IRExpr* e ) in putSReg() argument
569 stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) ); in putSReg()
1290 static const HChar* nameSReg ( UInt sreg ) in nameSReg() argument
1292 switch (sreg) { in nameSReg()
1424 Int sreg; in handleSegOverride() local
1433 case 0x3E: sreg = R_DS; break; in handleSegOverride()
[all …]
Dguest_amd64_toIR.c2214 static const HChar* nameSReg ( UInt sreg ) in nameSReg() argument
2216 switch (sreg) { in nameSReg()
/external/clang/lib/StaticAnalyzer/Core/
DMemRegion.cpp333 const MemRegion *sreg) { in ProfileRegion() argument
336 ID.AddPointer(sreg); in ProfileRegion()
/external/vixl/src/aarch32/
Dassembler-aarch32.cc18247 const SRegister& sreg = sreglist.GetFirstSRegister(); in vldm() local
18250 (write_back.GetWriteBackUint32() << 21) | sreg.Encode(22, 12) | in vldm()
18257 const SRegister& sreg = sreglist.GetFirstSRegister(); in vldm() local
18260 (write_back.GetWriteBackUint32() << 21) | sreg.Encode(22, 12) | in vldm()
18312 const SRegister& sreg = sreglist.GetFirstSRegister(); in vldmdb() local
18314 EmitT32_32(0xed300a00U | (rn.GetCode() << 16) | sreg.Encode(22, 12) | in vldmdb()
18322 const SRegister& sreg = sreglist.GetFirstSRegister(); in vldmdb() local
18325 sreg.Encode(22, 12) | (len & 0xff)); in vldmdb()
18376 const SRegister& sreg = sreglist.GetFirstSRegister(); in vldmia() local
18379 (write_back.GetWriteBackUint32() << 21) | sreg.Encode(22, 12) | in vldmia()
[all …]
/external/vixl/src/aarch64/
Dsimulator-aarch64.h1106 VIXL_DEPRECATED("ReadSRegister", float sreg(unsigned code) const) { in sreg() function