| /external/llvm/test/MC/Mips/ |
| D | micromips-shift-instructions.s | 15 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
20 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
23 # CHECK-EL: srlv $2, $2, $3 # encoding: [0x43,0x00,0x50,0x10]
35 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
40 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
43 # CHECK-EB: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50]
52 srlv $2, $3, $5
|
| D | rotations32.s | 11 # CHECK-32: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
18 # CHECK-32: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
53 # CHECK-32: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
59 # CHECK-32: srlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x06]
|
| D | rotations64.s | 11 # CHECK-64: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
18 # CHECK-64: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
53 # CHECK-64: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
59 # CHECK-64: srlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x06]
|
| D | mips-alu-instructions.s | 31 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
62 srlv $2, $3, $5
|
| D | mips64-alu-instructions.s | 29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
57 srlv $2, $3, $5
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | lshr.ll | 46 ; ALL: srlv $[[T0:[0-9]+]], $4, $5
59 ; ALL: srlv $[[T0:[0-9]+]], $4, $5
72 ; ALL: srlv $2, $4, $5
82 ; M2: srlv $[[T0:[0-9]+]], $4, $7
86 ; M2: srlv $[[T2:[0-9]+]], $5, $7
99 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
104 ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7
110 ; 32R6: srlv $[[T0:[0-9]+]], $5, $7
117 ; 32R6: srlv $[[T7:[0-9]+]], $4, $7
125 ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
[all …]
|
| D | ashr.ll | 88 ; M2: srlv $[[T2:[0-9]+]], $5, $7
101 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
119 ; 32R6: srlv $[[T6:[0-9]+]], $5, $7
131 ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
148 ; MMR6: srlv $[[T6:[0-9]+]], $5, $7
|
| D | shl.ll | 105 ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
118 ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
129 ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
144 ; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
155 ; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | vector-arith.ll | 308 ; MIPS32: srlv
309 ; MIPS32: srlv
310 ; MIPS32: srlv
311 ; MIPS32: srlv
312 ; MIPS32: srlv
313 ; MIPS32: srlv
314 ; MIPS32: srlv
315 ; MIPS32: srlv
316 ; MIPS32: srlv
317 ; MIPS32: srlv
[all …]
|
| D | nacl-atomic-intrinsics.ll | 371 ; MIPS32: srlv
412 ; MIPS32: srlv
649 ; MIPS32: srlv
691 ; MIPS32: srlv
817 ; MIPS32: srlv
859 ; MIPS32: srlv
902 ; MIPS32: srlv
944 ; MIPS32: srlv
1098 ; MIPS32: srlv
1141 ; MIPS32: srlv
[all …]
|
| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-LE | 908 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
909 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
910 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
911 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
912 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
913 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
914 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
915 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
916 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
917 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32-BE | 908 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
909 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
910 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
911 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
912 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
913 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
914 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
915 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
916 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
917 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32r2-BE | 1386 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
1387 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1388 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1389 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1390 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1391 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1392 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1393 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1394 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1395 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32r2-LE | 1386 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
1387 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1388 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1389 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1390 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1391 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1392 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1393 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1394 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1395 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | atomic.ll | 98 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
129 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
161 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
190 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
225 ; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 160 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
205 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
251 ; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]]
291 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
340 ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
384 ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
442 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
478 ; ALL: srlv $[[R9:[0-9]+]], $[[R6]], $
|
| D | srl2.ll | 13 ; 16: srlv ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 105 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
106 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 133 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
134 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 163 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
164 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 198 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
199 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 198 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
199 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 199 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
200 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 198 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
199 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| D | valid-mips1-el.txt | 100 0x06 0xc8 0x94 0x00 # CHECK: srlv $25, $20, $4
101 0x06 0xc8 0x94 0x00 # CHECK: srlv $25, $20, $4
|