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Searched refs:ssra (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-vsra.ll5 ;CHECK: ssra.8b
15 ;CHECK: ssra.4h
25 ;CHECK: ssra.2s
35 ;CHECK: ssra.16b
45 ;CHECK: ssra.8h
55 ;CHECK: ssra.4s
65 ;CHECK: ssra.2d
146 ; CHECK: ssra d0, d1, #63
Darm64-neon-simd-shift.ll103 ; CHECK: ssra {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
111 ; CHECK: ssra {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
119 ; CHECK: ssra {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
127 ; CHECK: ssra {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
135 ; CHECK: ssra {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
143 ; CHECK: ssra {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
151 ; CHECK: ssra {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #3
Darm64-vshift.ll1585 ;CHECK: ssra.8b v0, {{v[0-9]+}}, #1
1595 ;CHECK: ssra.4h v0, {{v[0-9]+}}, #1
1605 ;CHECK: ssra.2s v0, {{v[0-9]+}}, #1
1615 ;CHECK: ssra.16b v0, {{v[0-9]+}}, #1
1625 ;CHECK: ssra.8h v0, {{v[0-9]+}}, #1
1635 ;CHECK: ssra.4s v0, {{v[0-9]+}}, #1
1645 ;CHECK: ssra.2d v0, {{v[0-9]+}}, #1
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s45 ssra v0.8b, v1.8b, #3
46 ssra v0.4h, v1.4h, #3
47 ssra v0.2s, v1.2s, #3
48 ssra v0.16b, v1.16b, #3
49 ssra v0.8h, v1.8h, #3
50 ssra v0.4s, v1.4s, #3
51 ssra v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s36 ssra d18, d12, #21
Darm64-advsimd.s1559 ssra.16b v0, v0, #2
1560 ssra.4h v0, v0, #3
1561 ssra.8h v0, v0, #4
1562 ssra.2s v0, v0, #5
1563 ssra.4s v0, v0, #6
1564 ssra.2d v0, v0, #7
1565 ssra d0, d0, #64 define
1731 ; CHECK: ssra.16b v0, v0, #2 ; encoding: [0x00,0x14,0x0e,0x4f]
1732 ; CHECK: ssra.4h v0, v0, #3 ; encoding: [0x00,0x14,0x1d,0x0f]
1733 ; CHECK: ssra.8h v0, v0, #4 ; encoding: [0x00,0x14,0x1c,0x4f]
[all …]
Dneon-diagnostics.s1444 ssra v0.8b, v1.8h, #3
1445 ssra v0.4h, v1.4s, #3
1446 ssra v0.2s, v1.2d, #3
1447 ssra v0.16b, v1.16b, #9
1448 ssra v0.8h, v1.8h, #17
1449 ssra v0.4s, v1.4s, #33
1450 ssra v0.2d, v1.2d, #65
4953 ssra d18, d12, #99
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt756 # CHECK: ssra v0.8b, v1.8b, #3
757 # CHECK: ssra v0.4h, v1.4h, #3
758 # CHECK: ssra v0.2s, v1.2s, #3
759 # CHECK: ssra v0.16b, v1.16b, #3
760 # CHECK: ssra v0.8h, v1.8h, #3
761 # CHECK: ssra v0.4s, v1.4s, #3
762 # CHECK: ssra v0.2d, v1.2d, #3
1840 # CHECK: ssra d18, d12, #21
Darm64-advsimd.txt2134 # CHECK: ssra.16b v0, v0, #0x6
2135 # CHECK: ssra.4h v0, v0, #0xd
2136 # CHECK: ssra.8h v0, v0, #0xc
2137 # CHECK: ssra.2s v0, v0, #0x1b
2138 # CHECK: ssra.4s v0, v0, #0x1a
2139 # CHECK: ssra.2d v0, v0, #0x39
2140 # CHECK: ssra d0, d0, #0x40
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28506 ssra d5, d28, #1 db06ca6916e7597a81d889482e846e15 5566d2e7edae0b9d526fe09f6749ee50 000000000000…
28507 ssra d5, d28, #32 51b03d86f298d26c7e0396f7043b86ba 295f89e979ba378e2a3826dd9a9c5e0c 00000000000…
28508 ssra d5, d28, #64 2387050d33681aeb4b1e4c35739581ce f07c6d8d825d8ac36aebede07e0908ef 00000000000…
28512 ssra v6.2d, v27.2d, #1 0fe237f10d4ed3bbf24d8c2a7d4d7a8d 6a00191f2b9556bd39437ffabe90d96b 44e24…
28513 ssra v6.2d, v27.2d, #32 38d799de29038663d6ac752b7862e858 a61204904e93a121ee4f2768ad6ec54b 38d7…
28514 ssra v6.2d, v27.2d, #64 933267ae028f9f8f62331e3265d1d18c ad80341b46e0aac1e37c6713a51f844b 9332…
28515 ssra v6.4s, v27.4s, #1 82d1013ff9d27e1ff6c4e71fa37a9406 e02c09a0735cd27d77aaa0dc0682744b 72e70…
28516 ssra v6.4s, v27.4s, #16 6495c7726eac83f2f03d31d2923f92a9 9ef4e1ff36e678340ab831a33179f82a 6495…
28517 ssra v6.4s, v27.4s, #32 9a5f1a27bffd0feab27f5b2a93ff2a54 48ba1e17ee60fcc7fd887a4985e26dca 9a5f…
28518 ssra v6.2s, v27.2s, #1 830d5a3e4ea482e59c6bc6090599bce6 3d5c20cafba8bf17aff8dcab639f350a 00000…
[all …]
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1774 __ ssra(d12, d28, 44); in GenerateTestSequenceNEON() local
1775 __ ssra(v29.V16B(), v31.V16B(), 4); in GenerateTestSequenceNEON() local
1776 __ ssra(v3.V2D(), v0.V2D(), 24); in GenerateTestSequenceNEON() local
1777 __ ssra(v14.V2S(), v28.V2S(), 6); in GenerateTestSequenceNEON() local
1778 __ ssra(v18.V4H(), v8.V4H(), 7); in GenerateTestSequenceNEON() local
1779 __ ssra(v31.V4S(), v14.V4S(), 24); in GenerateTestSequenceNEON() local
1780 __ ssra(v28.V8B(), v26.V8B(), 5); in GenerateTestSequenceNEON() local
1781 __ ssra(v9.V8H(), v9.V8H(), 14); in GenerateTestSequenceNEON() local
Dtest-simulator-aarch64.cc4235 DEFINE_TEST_NEON_2OPIMM(ssra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4270 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(ssra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
/external/vixl/test/test-trace-reference/
Dlog-disasm1540 0x~~~~~~~~~~~~~~~~ 5f54178c ssra d12, d28, #44
1541 0x~~~~~~~~~~~~~~~~ 4f0c17fd ssra v29.16b, v31.16b, #4
1542 0x~~~~~~~~~~~~~~~~ 4f681403 ssra v3.2d, v0.2d, #24
1543 0x~~~~~~~~~~~~~~~~ 0f3a178e ssra v14.2s, v28.2s, #6
1544 0x~~~~~~~~~~~~~~~~ 0f191512 ssra v18.4h, v8.4h, #7
1545 0x~~~~~~~~~~~~~~~~ 4f2815df ssra v31.4s, v14.4s, #24
1546 0x~~~~~~~~~~~~~~~~ 0f0b175c ssra v28.8b, v26.8b, #5
1547 0x~~~~~~~~~~~~~~~~ 4f121529 ssra v9.8h, v9.8h, #14
Dlog-disasm-colour1540 0x~~~~~~~~~~~~~~~~ 5f54178c ssra d12, d28, #44
1541 0x~~~~~~~~~~~~~~~~ 4f0c17fd ssra v29.16b, v31.16b, #4
1542 0x~~~~~~~~~~~~~~~~ 4f681403 ssra v3.2d, v0.2d, #24
1543 0x~~~~~~~~~~~~~~~~ 0f3a178e ssra v14.2s, v28.2s, #6
1544 0x~~~~~~~~~~~~~~~~ 0f191512 ssra v18.4h, v8.4h, #7
1545 0x~~~~~~~~~~~~~~~~ 4f2815df ssra v31.4s, v14.4s, #24
1546 0x~~~~~~~~~~~~~~~~ 0f0b175c ssra v28.8b, v26.8b, #5
1547 0x~~~~~~~~~~~~~~~~ 4f121529 ssra v9.8h, v9.8h, #14
Dlog-all3903 0x~~~~~~~~~~~~~~~~ 5f54178c ssra d12, d28, #44
3905 0x~~~~~~~~~~~~~~~~ 4f0c17fd ssra v29.16b, v31.16b, #4
3907 0x~~~~~~~~~~~~~~~~ 4f681403 ssra v3.2d, v0.2d, #24
3909 0x~~~~~~~~~~~~~~~~ 0f3a178e ssra v14.2s, v28.2s, #6
3911 0x~~~~~~~~~~~~~~~~ 0f191512 ssra v18.4h, v8.4h, #7
3913 0x~~~~~~~~~~~~~~~~ 4f2815df ssra v31.4s, v14.4s, #24
3915 0x~~~~~~~~~~~~~~~~ 0f0b175c ssra v28.8b, v26.8b, #5
3917 0x~~~~~~~~~~~~~~~~ 4f121529 ssra v9.8h, v9.8h, #14
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc4888 ssra(vf, rd, rn, right_shift); in VisitNEONScalarShiftImmediate()
5015 ssra(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
Dassembler-aarch64.h2259 void ssra(const VRegister& vd, const VRegister& vn, int shift);
Dsimulator-aarch64.h2516 LogicVRegister ssra(VectorFormat vform,
Dmacro-assembler-aarch64.h2428 V(ssra, Ssra) \
Dlogic-aarch64.cc1811 LogicVRegister Simulator::ssra(VectorFormat vform, in ssra() function in vixl::aarch64::Simulator
Dassembler-aarch64.cc3731 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) { in ssra() function in vixl::aarch64::Assembler
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3728 void ssra(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4732 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4787 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",