/external/llvm/test/CodeGen/AArch64/ |
D | arm64-ldxr-stxr.ll | 99 %res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr) 109 %res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr) 117 ; CHECK: stxr w0, w1, [x2] 119 %res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr) 125 ; CHECK: stxr w0, x1, [x2] 126 %res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr) 130 declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) nounwind 131 declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) nounwind 132 declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*) nounwind 133 declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) nounwind
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D | arm64-atomic.ll | 10 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]] 28 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0] 65 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]] 124 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
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D | atomic-ops.ll | 87 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 147 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 247 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 307 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 407 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 483 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]] 557 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 679 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 968 ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-canonical-form.txt | 5 # CHECK: stxr w0, x0, [x0]
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D | arm64-memory.txt | 456 # CHECK: stxr w1, x4, [x3] 457 # CHECK: stxr w1, w4, [x3]
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D | basic-a64-instructions.txt | 1920 #CHECK: stxr w5, w6, [x17] 1921 #CHECK: stxr w1, x10, [x21] 1922 #CHECK: stxr w1, x10, [x21]
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/external/llvm/test/MC/AArch64/ |
D | arm64-memory.s | 468 stxr w1, x4, [x3] 469 stxr w1, w4, [x3] 475 ; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8] 476 ; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
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D | basic-a64-instructions.s | 2259 stxr wzr, w4, [sp] 2260 stxr w5, x6, [x7]
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/external/vixl/ |
D | README.md | 124 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
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/external/valgrind/docs/internals/ |
D | 3_11_BUGSTATUS.txt | 284 369459 valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)
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/external/vixl/test/aarch64/ |
D | test-disasm-aarch64.cc | 1778 COMPARE(stxr(w20, w21, MemOperand(x22)), "stxr w20, w21, [x22]"); in TEST() 1779 COMPARE(stxr(x23, w24, MemOperand(sp)), "stxr w23, w24, [sp]"); in TEST() 1780 COMPARE(stxr(w25, x26, MemOperand(x27)), "stxr w25, x26, [x27]"); in TEST() 1781 COMPARE(stxr(x28, x29, MemOperand(sp)), "stxr w28, x29, [sp]"); in TEST()
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D | test-trace-aarch64.cc | 338 __ stxr(w12, w13, MemOperand(x0)); in GenerateTestSequenceBase() local 339 __ stxr(x14, x15, MemOperand(x0)); in GenerateTestSequenceBase() local
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/external/vixl/src/aarch64/ |
D | assembler-aarch64.h | 1110 void stxr(const Register& rs, const Register& rt, const MemOperand& dst);
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D | macro-assembler-aarch64.h | 1896 stxr(rs, rt, dst); in Stxr()
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D | assembler-aarch64.cc | 1239 void Assembler::stxr(const Register& rs, in stxr() function in vixl::aarch64::Assembler
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/external/vixl/test/test-trace-reference/ |
D | log-disasm | 284 0x~~~~~~~~~~~~~~~~ 880c7c0d stxr w12, w13, [x0] 285 0x~~~~~~~~~~~~~~~~ c80e7c0f stxr w14, x15, [x0]
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D | log-disasm-colour | 284 0x~~~~~~~~~~~~~~~~ 880c7c0d stxr w12, w13, [x0] 285 0x~~~~~~~~~~~~~~~~ c80e7c0f stxr w14, x15, [x0]
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D | log-all | 702 0x~~~~~~~~~~~~~~~~ 880c7c0d stxr w12, w13, [x0] 704 0x~~~~~~~~~~~~~~~~ c80e7c0f stxr w14, x15, [x0]
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/external/vixl/doc/aarch64/ |
D | supported-instructions-aarch64.md | 1208 void stxr(const Register& rs, const Register& rt, const MemOperand& dst)
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 2458 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">; 2459 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
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/external/valgrind/ |
D | NEWS | 174 369459 valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)
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/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
D | Intrinsics.gen | 350 aarch64_stxr, // llvm.aarch64.stxr 6408 "llvm.aarch64.stxr", 14348 3, // llvm.aarch64.stxr
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/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
D | Intrinsics.gen | 341 aarch64_stxr, // llvm.aarch64.stxr 6365 "llvm.aarch64.stxr", 14250 3, // llvm.aarch64.stxr
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/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
D | Intrinsics.gen | 350 aarch64_stxr, // llvm.aarch64.stxr 6408 "llvm.aarch64.stxr", 14348 3, // llvm.aarch64.stxr
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/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
D | Intrinsics.gen | 350 aarch64_stxr, // llvm.aarch64.stxr 6408 "llvm.aarch64.stxr", 14348 3, // llvm.aarch64.stxr
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