| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | README-Thumb2.txt | 6 of tbb / tbh.
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| D | ARMInstrThumb2.td | 3160 "tbh", "\t$addr", []> {
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| /external/llvm/lib/Target/ARM/ |
| D | README-Thumb2.txt | 6 of tbb / tbh.
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| D | ARMInstrThumb2.td | 3575 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-jtb.ll | 3 ; Do not use tbb / tbh if any destination is before the jumptable.
9 ; CHECK-NOT: tbh
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| D | constant-islands-jump-table.ll | 5 ; CHECK-NOT: tbh
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| D | thumb2-tbh.ll | 3 ; Thumb2 target should reorder the bb's in order to use tbb / tbh.
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| D | thumb2-tbh.ll | 3 ; Thumb2 target should reorder the bb's in order to use tbb / tbh.
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| D | thumb2-jtb.ll | 3 ; Do not use tbb / tbh if any destination is before the jumptable.
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb-tests.txt | 173 # CHECK: tbh [r5, r4, lsl #1]
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| D | thumb2.txt | 2117 # CHECK: tbh [r3, r8, lsl #1]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-tests.txt | 173 # CHECK: tbh [r5, r4, lsl #1]
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| D | thumb2.txt | 2268 # CHECK: tbh [r3, r8, lsl #1]
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| /external/vixl/doc/aarch32/design/ |
| D | literal-pool-aarch32.md | 44 branch (like b, tbb/tbh, ...)
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| D | code-generation-aarch32.md | 55 example, `vldr` has a range of about 1KB, but `tbh` can easily exceed this
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2747 tbh [r3, r8, lsl #1]
2754 @ CHECK: tbh [r3, r8, lsl #1] @ encoding: [0xd3,0xe8,0x18,0xf0]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3518 void tbh(Condition cond, Register rn, Register rm);
3519 void tbh(Register rn, Register rm) { tbh(al, rn, rm); } in tbh() function
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| D | disasm-aarch32.h | 1225 void tbh(Condition cond, Register rn, Register rm);
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| D | assembler-aarch32.cc | 11695 void Assembler::tbh(Condition cond, Register rn, Register rm) { in tbh() function in vixl::aarch32::Assembler
11707 Delegate(kTbh, &Assembler::tbh, cond, rn, rm); in tbh()
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| D | disasm-aarch32.cc | 3294 void Disassembler::tbh(Condition cond, Register rn, Register rm) { in tbh() function in vixl::aarch32::Disassembler
10424 tbh(CurrentCond(), in DecodeT32()
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3244 tbh [r3, r8, lsl #1]
3251 @ CHECK: tbh [r3, r8, lsl #1] @ encoding: [0xd3,0xe8,0x18,0xf0]
|