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/external/llvm/test/CodeGen/Mips/
Ddivrem.ll35 ; ACC32-TRAP: teq $5, $zero, 7
38 ; ACC64-TRAP: teq $5, $zero, 7
41 ; GPR32-TRAP: teq $5, $zero, 7
44 ; GPR64-TRAP: teq $5, $zero, 7
46 ; NOCHECK-NOT: teq
62 ; ACC32-TRAP: teq $5, $zero, 7
65 ; ACC64-TRAP: teq $5, $zero, 7
68 ; GPR32-TRAP: teq $5, $zero, 7
71 ; GPR64-TRAP: teq $5, $zero, 7
73 ; NOCHECK-NOT: teq
[all …]
Dmips64instrs.ll120 ; ACCMULDIV: teq $[[T1]], $zero, 7
124 ; GPRMULDIV: teq $[[T1]], $zero, 7
141 ; ACCMULDIV: teq $[[T1]], $zero, 7
145 ; GPRMULDIV: teq $[[T1]], $zero, 7
158 ; ACCMULDIV: teq $5, $zero, 7
162 ; GPRMULDIV: teq $5, $zero, 7
173 ; ACCMULDIV: teq $5, $zero, 7
177 ; GPRMULDIV: teq $5, $zero, 7
Dassertzext-trunc.ll24 ; PRE-R6: teq $5, $zero, 7
29 ; R6: teq $5, $zero, 7
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dudiv.ll41 ; NOT-R6: teq $5, $zero, 7
45 ; R6: teq $5, $zero, 7
48 ; MMR3: teq $5, $zero, 7
52 ; MMR6: teq $5, $zero, 7
63 ; NOT-R6: teq $5, $zero, 7
67 ; R6: teq $5, $zero, 7
70 ; MMR3: teq $5, $zero, 7
74 ; MMR6: teq $5, $zero, 7
85 ; NOT-R6: teq $5, $zero, 7
89 ; R6: teq $5, $zero, 7
[all …]
Dsrem.ll41 ; NOT-R6: teq $5, $zero, 7
47 ; R6: teq $5, $zero, 7
52 ; MMR3: teq $5, $zero, 7
58 ; MMR6: teq $5, $zero, 7
71 ; NOT-R2-R6: teq $5, $zero, 7
77 ; R2-R5: teq $5, $zero, 7
82 ; R6: teq $5, $zero, 7
86 ; MMR3: teq $5, $zero, 7
91 ; MMR6: teq $5, $zero, 7
103 ; NOT-R2-R6: teq $5, $zero, 7
[all …]
Dsdiv.ll41 ; NOT-R6: teq $5, $zero, 7
48 ; R6: teq $5, $zero, 7
54 ; MMR3: teq $5, $zero, 7
60 ; MMR6: teq $5, $zero, 7
73 ; NOT-R2-R6: teq $5, $zero, 7
80 ; R2-R5: teq $5, $zero, 7
86 ; R6: teq $5, $zero, 7
91 ; MMR3: teq $5, $zero, 7
96 ; MMR6: teq $5, $zero, 7
108 ; NOT-R2-R6: teq $5, $zero, 7
[all …]
Durem.ll43 ; NOT-R6: teq $[[T0]], $zero, 7
51 ; R6: teq $[[T0]], $zero, 7
58 ; MMR3: teq $[[T0]], $zero, 7
66 ; MMR6: teq $[[T0]], $zero, 7
81 ; NOT-R2-R6: teq $[[T0]], $zero, 7
89 ; R2-R5: teq $[[T0]], $zero, 7
96 ; R6: teq $[[T0]], $zero, 7
102 ; MMR3: teq $[[T0]], $zero, 7
109 ; MMR6: teq $[[T0]], $zero, 7
123 ; NOT-R2-R6: teq $[[T0]], $zero, 7
[all …]
/external/llvm/test/MC/Mips/
Dmacro-ddiv.s74 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
80 # CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
84 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
90 # CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
94 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
97 # CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
103 # CHECK-TRAP: teq $zero, $1, 6 # encoding: [0x00,0x01,0x01,0xb4]
107 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
110 # CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
116 # CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
[all …]
Dmacro-div.s61 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
66 # CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
70 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
75 # CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
79 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
88 # CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
93 # CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
97 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
100 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
Dmacro-ddivu.s58 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
63 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
68 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
73 # CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
78 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
83 # CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
88 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
93 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
Dmips-control-instructions.s18 # CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
19 # CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
49 # CHECK64: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
50 # CHECK64: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
83 teq $0,$3
84 teq $0,$3,1
Dmacro-divu.s52 # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
57 # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
62 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
73 # CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
78 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
83 # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
Dmicromips-trap-instructions.s12 # CHECK-EL: teq $8, $9 # encoding: [0x28,0x01,0x3c,0x00]
27 # CHECK-EB: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
39 teq $8, $9, 0
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-teq2.ll8 ; CHECK: teq.w {{.*}}, r1
16 ; CHECK: teq.w {{.*}}, r1
24 ; CHECK: teq.w {{.*}}, r1, lsl #5
33 ; CHECK: teq.w {{.*}}, r1, lsr #6
42 ; CHECK: teq.w {{.*}}, r1, asr #7
51 ; CHECK: teq.w {{.*}}, {{.*}}, ror #8
Dthumb2-teq.ll13 ; CHECK: teq.w {{.*}}, #187
22 ; CHECK: teq.w {{.*}}, #11141290
31 ; CHECK: teq.w {{.*}}, #-872363008
40 ; CHECK: teq.w {{.*}}, #-572662307
56 ; CHECK: teq.w {{.*}}, #1114112
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-teq2.ll8 ; CHECK: teq.w r0, r1
16 ; CHECK: teq.w r0, r1
24 ; CHECK: teq.w r0, r1, lsl #5
33 ; CHECK: teq.w r0, r1, lsr #6
42 ; CHECK: teq.w r0, r1, asr #7
51 ; CHECK: teq.w r0, r0, ror #8
Dthumb2-teq.ll13 ; CHECK: teq.w r0, #187
22 ; CHECK: teq.w r0, #11141290
31 ; CHECK: teq.w r0, #-872363008
40 ; CHECK: teq.w r0, #-572662307
56 ; CHECK: teq.w r0, #1114112
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dsdiv.ll25 ; MIPS32: teq
42 ; MIPS32: teq
56 ; MIPS32: teq
72 ; MIPS32: teq
89 ; MIPS32: teq
103 ; MIPS32: teq
Dunreachable.ll62 ; MIPS32: teq zero,zero
68 ; MIPS32-O2: teq zero,zero
Darith.ll172 ; MIPS32: teq [[REG]],zero,0x7
193 ; MIPS32: teq [[REG]],zero,0x7
217 ; MIPS32: teq [[REG]],zero,0x7
239 ; MIPS32: teq [[REG]],zero,0x7
262 ; MIPS32: teq [[REG]],zero,0x7
/external/swiftshader/third_party/subzero/tests_lit/assembler/mips32/
Dencoding_trap.ll31 ; ASM: teq $zero, $zero, 0
34 ; DIS-NEXT: 0: 00000034 teq zero,zero
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid-wrong-error.s10 teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
11 teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
12 …teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Ddiv1.ll25 ; CHECK-DAG: teq $[[K]], $zero, 7
47 ; CHECK-DAG: teq $[[K]], $zero, 7
Drem1.ll25 ; CHECK-DAG: teq $[[K]], $zero, 7
48 ; CHECK-DAG: teq $[[K]], $zero, 7
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid-wrong-error.s18 teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
19 teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
20 …teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…

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