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Searched refs:tiling (Results 1 – 25 of 167) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_regions.c111 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal() argument
125 region->tiling = tiling; in intel_region_alloc_internal()
133 uint32_t tiling, in intel_region_alloc() argument
147 &tiling, &aligned_pitch, flags); in intel_region_alloc()
152 aligned_pitch, tiling, buffer); in intel_region_alloc()
183 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
188 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); in intel_region_alloc_for_handle()
197 width, height, pitch, tiling, buffer); in intel_region_alloc_for_handle()
218 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_fd() local
223 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); in intel_region_alloc_for_fd()
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/external/mesa3d/src/intel/isl/
Disl.c128 enum isl_tiling tiling, in isl_tiling_get_info() argument
135 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) { in isl_tiling_get_info()
141 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0); in isl_tiling_get_info()
143 return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info); in isl_tiling_get_info()
146 switch (tiling) { in isl_tiling_get_info()
190 bool is_Ys = tiling == ISL_TILING_Ys; in isl_tiling_get_info()
239 .tiling = tiling, in isl_tiling_get_info()
254 enum isl_tiling *tiling) in isl_surf_choose_tiling() argument
262 *tiling = ISL_TILING_HIZ; in isl_surf_choose_tiling()
270 *tiling = ISL_TILING_CCS; in isl_surf_choose_tiling()
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Disl_gen9.c35 enum isl_tiling tiling, in gen9_calc_std_image_alignment_sa() argument
41 assert(isl_tiling_is_std_y(tiling)); in gen9_calc_std_image_alignment_sa()
44 const uint32_t is_Ys = tiling == ISL_TILING_Ys; in gen9_calc_std_image_alignment_sa()
102 enum isl_tiling tiling, in isl_gen9_choose_image_alignment_el() argument
168 if (isl_tiling_is_std_y(tiling)) { in isl_gen9_choose_image_alignment_el()
170 gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, in isl_gen9_choose_image_alignment_el()
199 isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout, in isl_gen9_choose_image_alignment_el()
Disl_gen7.c30 enum isl_tiling tiling, in isl_gen7_choose_msaa_layout() argument
86 if (tiling == ISL_TILING_LINEAR) in isl_gen7_choose_msaa_layout()
323 enum isl_tiling tiling) in gen7_choose_valign_el() argument
348 tiling == ISL_TILING_Y0)) { in gen7_choose_valign_el()
393 enum isl_tiling tiling, in isl_gen7_choose_image_alignment_el() argument
408 .h = gen7_choose_valign_el(dev, info, tiling), in isl_gen7_choose_image_alignment_el()
Disl_storage_image.c246 switch (surf->tiling) { in isl_surf_fill_image_param()
253 param->tiling[0] = isl_log2u(512 / cpp); in isl_surf_fill_image_param()
254 param->tiling[1] = isl_log2u(8); in isl_surf_fill_image_param()
271 param->tiling[0] = isl_log2u(16 / cpp); in isl_surf_fill_image_param()
272 param->tiling[1] = isl_log2u(32); in isl_surf_fill_image_param()
292 param->tiling[2] = (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ? in isl_surf_fill_image_param()
Disl_gen4.c30 enum isl_tiling tiling, in isl_gen4_choose_msaa_layout() argument
43 enum isl_tiling tiling, in isl_gen4_choose_image_alignment_el() argument
50 assert(!isl_tiling_is_std_y(tiling)); in isl_gen4_choose_image_alignment_el()
Disl_gen6.c30 enum isl_tiling tiling, in isl_gen6_choose_msaa_layout() argument
59 if (tiling == ISL_TILING_LINEAR) in isl_gen6_choose_msaa_layout()
71 enum isl_tiling tiling, in isl_gen6_choose_image_alignment_el() argument
Disl_gen8.c30 enum isl_tiling tiling, in isl_gen8_choose_msaa_layout() argument
185 enum isl_tiling tiling, in isl_gen8_choose_image_alignment_el() argument
193 assert(!isl_tiling_is_std_y(tiling)); in isl_gen8_choose_image_alignment_el()
Disl_gen8.h36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
Disl_gen4.h36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
/external/mesa3d/src/gallium/drivers/ilo/core/
Dilo_builder_blt.h57 enum gen_surface_tiling tiling; member
174 if (dst->tiling != GEN6_TILING_NONE) { in gen6_XY_COLOR_BLT()
177 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y); in gen6_XY_COLOR_BLT()
178 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512; in gen6_XY_COLOR_BLT()
278 if (dst->tiling != GEN6_TILING_NONE) { in gen6_XY_SRC_COPY_BLT()
281 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y); in gen6_XY_SRC_COPY_BLT()
282 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512; in gen6_XY_SRC_COPY_BLT()
287 if (src->tiling != GEN6_TILING_NONE) { in gen6_XY_SRC_COPY_BLT()
290 assert(src->tiling == GEN6_TILING_X || src->tiling == GEN6_TILING_Y); in gen6_XY_SRC_COPY_BLT()
291 src_align = (src->tiling == GEN6_TILING_Y) ? 128 : 512; in gen6_XY_SRC_COPY_BLT()
Dilo_image.c48 enum gen_surface_tiling tiling; member
330 enum gen_surface_tiling tiling) in image_get_gen7_mcs_enable() argument
372 tiling == GEN6_TILING_NONE || in image_get_gen7_mcs_enable()
445 enum gen_surface_tiling tiling, in image_get_gen7_alignments() argument
522 (tiling == GEN6_TILING_Y && info->bind_surface_dp_render)); in image_get_gen7_alignments()
554 layout->tiling = image_get_gen6_tiling(dev, info, layout->valid_tilings); in image_init_gen6_hardware_layout()
559 image_get_gen7_mcs_enable(dev, info, layout->tiling)) in image_init_gen6_hardware_layout()
565 image_get_gen7_alignments(dev, info, layout->tiling, in image_init_gen6_hardware_layout()
586 layout->tiling = GEN6_TILING_NONE; in image_init_gen6_transfer_layout()
1030 layout->tiling == GEN6_TILING_NONE) in image_set_gen6_bo_size()
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/external/deqp/external/vulkancts/modules/vulkan/ycbcr/
DvktYCbCrFormatTests.cpp78 VkImageTiling tiling, in createTestImage() argument
92 tiling, in createTestImage()
230 VkImageTiling tiling; member
243 , tiling (tiling_) in TestParameters()
252 , tiling (VK_IMAGE_TILING_OPTIMAL) in TestParameters()
277 checkImageSupport(context, params.format, params.flags, params.tiling); in checkSupport()
305 const VkImageTiling tiling = params.tiling; in testFormat() local
308 …const Unique<VkImage> image (createTestImage(vkd, device, format, size, createFlags, tiling, … in testFormat()
507 const VkImageTiling tiling = tilings[tilingNdx].value; in populatePerFormatGroup() local
513 …up, name, "", initPrograms, testFormat, TestParameters(format, size, 0u, tiling, shaderType, false… in populatePerFormatGroup()
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/external/mesa3d/src/gallium/drivers/ilo/
Dilo_resource.c220 winsys_to_surface_tiling(enum intel_tiling_mode tiling) in winsys_to_surface_tiling() argument
222 switch (tiling) { in winsys_to_surface_tiling()
236 surface_to_winsys_tiling(enum gen_surface_tiling tiling) in surface_to_winsys_tiling() argument
238 switch (tiling) { in surface_to_winsys_tiling()
301 if (bo && (tex->image.tiling == GEN6_TILING_X || in tex_create_bo()
302 tex->image.tiling == GEN6_TILING_Y)) { in tex_create_bo()
303 const enum intel_tiling_mode tiling = in tex_create_bo() local
304 surface_to_winsys_tiling(tex->image.tiling); in tex_create_bo()
306 if (intel_bo_set_tiling(bo, tiling, tex->image.bo_stride)) { in tex_create_bo()
442 enum intel_tiling_mode tiling; in tex_import_handle() local
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Dilo_blitter_blt.c253 if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8) in tex_clear_region()
265 dst.tiling = dst_tex->image.tiling; in tex_clear_region()
269 dst_tex->vma.bo, dst_tex->image.tiling, NULL, GEN6_TILING_NONE); in tex_clear_region()
313 if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8 || in tex_copy_region()
314 src_tex->image.tiling == GEN8_TILING_W || src_tex->separate_s8) in tex_copy_region()
354 dst.tiling = dst_tex->image.tiling; in tex_copy_region()
359 src.tiling = src_tex->image.tiling; in tex_copy_region()
363 dst.bo, dst.tiling, src.bo, src.tiling); in tex_copy_region()
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_cl_dump.c114 const char *tiling = "???"; in dump_loadstore_general() local
117 tiling = "linear"; in dump_loadstore_general()
120 tiling = "T"; in dump_loadstore_general()
123 tiling = "LT"; in dump_loadstore_general()
142 buffer, tiling); in dump_loadstore_general()
315 const char *tiling = "???"; in dump_VC4_PACKET_TILE_RENDERING_MODE_CONFIG() local
318 tiling = "linear"; in dump_VC4_PACKET_TILE_RENDERING_MODE_CONFIG()
321 tiling = "T"; in dump_VC4_PACKET_TILE_RENDERING_MODE_CONFIG()
324 tiling = "LT"; in dump_VC4_PACKET_TILE_RENDERING_MODE_CONFIG()
331 format, tiling, in dump_VC4_PACKET_TILE_RENDERING_MODE_CONFIG()
/external/vulkan-validation-layers/loader/
Dextensions.c35 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, in vkGetPhysicalDeviceExternalImageFormatPropertiesNV() argument
44 unwrapped_phys_dev, format, type, tiling, usage, flags, in vkGetPhysicalDeviceExternalImageFormatPropertiesNV()
51 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, in terminator_GetPhysicalDeviceExternalImageFormatPropertiesNV() argument
72 phys_dev->phys_dev, format, type, tiling, usage, flags, in terminator_GetPhysicalDeviceExternalImageFormatPropertiesNV()
77 phys_dev->phys_dev, format, type, tiling, usage, flags, in terminator_GetPhysicalDeviceExternalImageFormatPropertiesNV()
/external/mesa3d/src/gallium/winsys/intel/drm/
Dintel_drm_winsys.c95 uint32_t tiling = I915_TILING_X, swizzle; in test_address_swizzling() local
99 "address swizzling test", 64, 64, 4, &tiling, &pitch, 0); in test_address_swizzling()
101 drm_intel_bo_get_tiling(bo, &tiling, &swizzle); in test_address_swizzling()
309 enum intel_tiling_mode *tiling, in intel_winsys_import_handle() argument
350 *tiling = real_tiling; in intel_winsys_import_handle()
359 enum intel_tiling_mode tiling, in intel_winsys_export_handle() argument
490 enum intel_tiling_mode tiling, in intel_bo_set_tiling() argument
493 uint32_t real_tiling = tiling; in intel_bo_set_tiling()
496 switch (tiling) { in intel_bo_set_tiling()
510 if (err || real_tiling != tiling) { in intel_bo_set_tiling()
/external/skia/src/gpu/vk/
DGrVkImage.h98 void setNewResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling);
115 Resource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) in Resource() argument
120 , fImageTiling(tiling) {} in Resource()
155 BorrowedResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) in BorrowedResource() argument
156 : Resource(image, alloc, tiling) { in BorrowedResource()
/external/libdrm/tegra/
Dtegra.c341 struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_get_tiling() argument
358 if (tiling) { in drm_tegra_bo_get_tiling()
359 tiling->mode = args.mode; in drm_tegra_bo_get_tiling()
360 tiling->value = args.value; in drm_tegra_bo_get_tiling()
367 const struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_set_tiling() argument
378 args.mode = tiling->mode; in drm_tegra_bo_set_tiling()
379 args.value = tiling->value; in drm_tegra_bo_set_tiling()
/external/mesa3d/src/gallium/drivers/i915/
Di915_state_static.c79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling) in buf_3d_tiling_bits() argument
83 switch (tiling) { in buf_3d_tiling_bits()
110 buf_3d_tiling_bits(tex->tiling); in update_framebuffer()
135 buf_3d_tiling_bits(tex->tiling); in update_framebuffer()
218 if (is->is_i945 && tex->tiling != I915_TILE_NONE in update_dst_buf_vars()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_mipmap_tree.c106 unsigned tiling) in intel_tiling_supports_non_msrt_mcs() argument
116 return tiling == I915_TILING_Y; in intel_tiling_supports_non_msrt_mcs()
118 return tiling != I915_TILING_NONE; in intel_tiling_supports_non_msrt_mcs()
586 intel_get_tile_dims(mt->tiling, mt->tr_mode, mt->cpp, in intel_get_yf_ys_bo_size()
639 if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) in miptree_create()
640 mt->tiling = I915_TILING_Y; in miptree_create()
661 mt->cpp, &mt->tiling, &pitch, in miptree_create()
666 mt->cpp, &mt->tiling, &pitch, in miptree_create()
699 mt->tiling == I915_TILING_Y) { in intel_miptree_create()
707 mt->tiling = I915_TILING_X; in intel_miptree_create()
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Dintel_pixel_read.c132 (irb->mt->tiling != I915_TILING_X && in intel_readpixels_tiled_memcpy()
133 irb->mt->tiling != I915_TILING_Y)) { in intel_readpixels_tiled_memcpy()
183 format, type, rb->Format, irb->mt->tiling, in intel_readpixels_tiled_memcpy()
194 irb->mt->tiling, in intel_readpixels_tiled_memcpy()
/external/mesa3d/src/intel/vulkan/
Danv_gem.c176 uint32_t gem_handle, uint32_t stride, uint32_t tiling) in anv_gem_set_tiling() argument
186 .tiling_mode = tiling, in anv_gem_set_tiling()
214 anv_gem_get_bit6_swizzle(int fd, uint32_t tiling) in anv_gem_get_bit6_swizzle() argument
236 .tiling_mode = tiling, in anv_gem_get_bit6_swizzle()
237 .stride = tiling == I915_TILING_X ? 512 : 128, in anv_gem_get_bit6_swizzle()
/external/mesa3d/src/gallium/winsys/i915/drm/
Di915_drm_buffer.c57 enum i915_winsys_buffer_tile *tiling, in i915_drm_buffer_create_tiled() argument
63 uint32_t tiling_mode = *tiling; in i915_drm_buffer_create_tiled()
81 *tiling = tiling_mode; in i915_drm_buffer_create_tiled()
94 enum i915_winsys_buffer_tile *tiling, in i915_drm_buffer_from_handle() argument
129 *tiling = tile; in i915_drm_buffer_from_handle()

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