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Searched refs:tmp116 (Results 1 – 25 of 32) sorted by relevance

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/external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dfft.c75 int16_t tmp116, tmp216; in WebRtcIsacfix_FftRadix16Fastest() local
179 tmp116 = ajQx >> 1; in WebRtcIsacfix_FftRadix16Fastest()
181 akQx = akQx - tmp116; in WebRtcIsacfix_FftRadix16Fastest()
183 tmp116 = RexQx[k1] - RexQx[k2]; in WebRtcIsacfix_FftRadix16Fastest()
186 ajQx = (int16_t)WEBRTC_SPL_MUL_16_16_RSFT(sss60Q14, tmp116, 14); // Q14*Qx>>14 = Qx in WebRtcIsacfix_FftRadix16Fastest()
/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
D2008-01-25-dag-combine-mul.ll20 %tmp116 = add i64 %tmp112, 0 ; <i64> [#uses=1]
21 %tmp117 = add i64 %tmp103, %tmp116 ; <i64> [#uses=1]
/external/llvm/test/CodeGen/Generic/
D2008-01-25-dag-combine-mul.ll20 %tmp116 = add i64 %tmp112, 0 ; <i64> [#uses=1]
21 %tmp117 = add i64 %tmp103, %tmp116 ; <i64> [#uses=1]
/external/llvm/test/CodeGen/PowerPC/
D2009-09-18-carrybit.ll40 %tmp116 = or i32 %tmp114, %tmp115 ; <i32> [#uses=1]
41 %tmp160 = zext i32 %tmp116 to i64 ; <i64> [#uses=1]
Dresolvefi-basereg.ll31 %agg.tmp116 = alloca %struct.S1998, align 16
344 %67 = bitcast %struct.S1998* %agg.tmp116 to i8*
352 …call void (i32, ...) @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struc…
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
D2009-09-18-carrybit.ll40 %tmp116 = or i32 %tmp114, %tmp115 ; <i32> [#uses=1]
41 %tmp160 = zext i32 %tmp116 to i64 ; <i64> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2007-08-15-ReuseBug.ll47 %tmp116.i = getelementptr i8** %argv_addr.2321.0.i, i32 2 ; <i8**> [#uses=1]
48 %tmp117.i = load i8** %tmp116.i ; <i8*> [#uses=1]
Ddebug-info-branch-folding.ll30 %tmp116 = extractelement <4 x float> %add20, i32 1
31 %conv6.i76 = fpext float %tmp116 to double, !dbg !45
/external/llvm/test/CodeGen/ARM/
Ddebug-info-branch-folding.ll32 %tmp116 = extractelement <4 x float> %add20, i32 1
33 %conv6.i76 = fpext float %tmp116 to double, !dbg !45
D2007-08-15-ReuseBug.ll47 %tmp116.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 2 ; <i8**> [#uses=1]
48 %tmp117.i = load i8*, i8** %tmp116.i ; <i8*> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2009-09-10-SpillComments.ll96 %tmp116 = icmp ult i32 %tmp104, %tmp115 ; <i1> [#uses=1]
97 br i1 %tmp116, label %bb73, label %bb123
Dmultiple-loop-post-inc.ll110 %tmp116 = add i64 %tmp115, %tmp104 ; <i64> [#uses=2]
111 %scevgep117 = getelementptr float* %I, i64 %tmp116 ; <float*> [#uses=1]
120 %scevgep128 = getelementptr float* %O, i64 %tmp116 ; <float*> [#uses=1]
D2009-03-23-MultiUseSched.ll128 %tmp116 = add i64 %tmp99, %tmp86 ; <i64> [#uses=1]
129 %tmp117 = add i64 %tmp116, %tmp112 ; <i64> [#uses=1]
D2007-08-09-IllegalX86-64Asm.ll170 %tmp116 = load i64* %tmp115 ; <i64> [#uses=1]
171 %tmp117 = add i64 %tmp116, -1 ; <i64> [#uses=2]
/external/llvm/test/CodeGen/X86/
D2009-09-10-SpillComments.ll96 %tmp116 = icmp ult i32 %tmp104, %tmp115 ; <i1> [#uses=1]
97 br i1 %tmp116, label %bb73, label %bb123
Dpr13209.ll29 %tmp116 = load i8*, i8** %x, align 8
Dmultiple-loop-post-inc.ll114 %tmp116 = add i64 %tmp115, %tmp104 ; <i64> [#uses=2]
115 %scevgep117 = getelementptr float, float* %I, i64 %tmp116 ; <float*> [#uses=1]
124 %scevgep128 = getelementptr float, float* %O, i64 %tmp116 ; <float*> [#uses=1]
Dpr24139.ll125 %tmp116 = fadd <4 x float> %tmp102, %tmp115
131 …%tmp122 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp114, <4 x float> %tmp116,…
D2009-03-23-MultiUseSched.ll129 %tmp116 = add i64 %tmp99, %tmp86 ; <i64> [#uses=1]
130 %tmp117 = add i64 %tmp116, %tmp112 ; <i64> [#uses=1]
D2007-08-09-IllegalX86-64Asm.ll170 %tmp116 = load i64, i64* %tmp115 ; <i64> [#uses=1]
171 %tmp117 = add i64 %tmp116, -1 ; <i64> [#uses=2]
/external/llvm/test/Transforms/LoopStrengthReduce/
D2012-07-18-LimitReassociate.ll256 %tmp116 = phi i64 [ %tmp122, %bb121 ], [ 0, %bb113 ]
258 %tmp118 = trunc i64 %tmp116 to i32
266 %tmp122 = add i64 %tmp116, 1
/external/swiftshader/third_party/LLVM/test/Transforms/MemCpyOpt/
Dform-memset.ll106 %tmp116 = getelementptr [8 x %struct.MV]* %up_mvd, i32 0, i32 2, i32 1 ; <i16*> [#uses=1]
107 store i16 0, i16* %tmp116, align 2
/external/llvm/test/CodeGen/AMDGPU/
Dsgpr-copy.ll152 %tmp116 = bitcast i32 %tmp115 to float
153 …ort(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp114, float %tmp116, float %tmp114, float %tmp116)
Dvgpr-spill-emergency-stack-slot.ll139 %tmp116 = phi float [ 0.000000e+00, %bb ], [ %tmp381, %bb157 ]
205 …rt(i32 15, i32 0, i32 0, i32 54, i32 0, float %tmp113, float %tmp114, float %tmp115, float %tmp116)
313 %tmp252 = insertelement <128 x float> %tmp251, float %tmp116, i32 90
/external/llvm/test/Transforms/MemCpyOpt/
Dform-memset.ll106 …%tmp116 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 2, i32 1 ; <i16*>…
107 store i16 0, i16* %tmp116, align 2

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