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/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
D2007-12-18-AddSelCmpSub.ll5 %tmp15 = sub i32 99, %a ; <i32> [#uses=2]
6 %tmp16 = icmp slt i32 %tmp15, 0 ; <i1> [#uses=1]
7 %smax = select i1 %tmp16, i32 0, i32 %tmp15 ; <i32> [#uses=1]
15 %tmp15 = sub i32 99, %a ; <i32> [#uses=2]
16 %tmp16 = icmp slt i32 %tmp15, 0 ; <i1> [#uses=1]
17 %smax = select i1 %tmp16, i32 0, i32 %tmp15 ; <i32> [#uses=1]
24 %tmp15 = sub i32 99, %a ; <i32> [#uses=1]
26 %smax = select i1 %tmp16, i32 0, i32 %tmp15 ; <i32> [#uses=1]
/external/llvm/test/Transforms/InstCombine/
D2007-12-18-AddSelCmpSub.ll5 %tmp15 = sub i32 99, %a ; <i32> [#uses=2]
6 %tmp16 = icmp slt i32 %tmp15, 0 ; <i1> [#uses=1]
7 %smax = select i1 %tmp16, i32 0, i32 %tmp15 ; <i32> [#uses=1]
15 %tmp15 = sub i32 99, %a ; <i32> [#uses=2]
16 %tmp16 = icmp slt i32 %tmp15, 0 ; <i1> [#uses=1]
17 %smax = select i1 %tmp16, i32 0, i32 %tmp15 ; <i32> [#uses=1]
24 %tmp15 = sub i32 99, %a ; <i32> [#uses=1]
26 %smax = select i1 %tmp16, i32 0, i32 %tmp15 ; <i32> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2008-02-22-ReMatBug.ll38 %tmp15.reg2mem.0 = sdiv i32 %size, 2 ; <i32> [#uses=7]
39 %tmp85 = sub i32 %center_y, %tmp15.reg2mem.0 ; <i32> [#uses=2]
40 %tmp88 = sub i32 %center_x, %tmp15.reg2mem.0 ; <i32> [#uses=2]
41 …%tmp92 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 %tmp88, i32 %tmp85, …
44 …%tmp110 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 0, i32 %tmp85, i32 …
45 %tmp122 = add i32 %tmp15.reg2mem.0, %center_y ; <i32> [#uses=2]
46 …%tmp129 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 0, i32 %tmp122, i32…
47 …%tmp147 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 %tmp88, i32 %tmp122…
Dvec_fneg.ll4 …%tmp15 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -…
5 ret <4 x float> %tmp15
9 %tmp15 = fsub <4 x float> zeroinitializer, %Q
10 ret <4 x float> %tmp15
D2006-10-10-FindModifiedNodeSlotBug.ll15 %tmp15 = lshr i32 %tmp14, 31 ; <i32> [#uses=1]
16 %tmp15.upgrd.3 = trunc i32 %tmp15 to i8 ; <i8> [#uses=1]
17 %tmp16 = icmp ne i8 %tmp15.upgrd.3, 0 ; <i1> [#uses=1]
D2009-04-25-CoalescerBug.ll9 %tmp15 = load i32* %tmp13 ; <i32> [#uses=2]
10 %bf.lo = lshr i32 %tmp15, 1 ; <i32> [#uses=1]
13 %bf.lo.cleared25 = and i32 %tmp15, 1 ; <i32> [#uses=1]
Dfp-stack.ll9 %tmp15 = load x86_fp80* undef ; <x86_fp80> [#uses=2]
14 %cmp139 = fcmp ogt x86_fp80 %tmp15, %tmp6 ; <i1> [#uses=1]
15 %maxdiag.0 = select i1 %cmp139, x86_fp80 %tmp15, x86_fp80 %tmp6 ; <x86_fp80> [#uses=1]
Dx86-64-sret-return.ll34 %tmp15 = getelementptr %struct.foo* %memtmp, i32 0, i32 0 ; <[4 x i64]*> [#uses=4]
36 %tmp17 = getelementptr [4 x i64]* %tmp15, i32 0, i32 0 ; <i64*> [#uses=1]
40 %tmp20 = getelementptr [4 x i64]* %tmp15, i32 0, i32 1 ; <i64*> [#uses=1]
44 %tmp23 = getelementptr [4 x i64]* %tmp15, i32 0, i32 2 ; <i64*> [#uses=1]
48 %tmp26 = getelementptr [4 x i64]* %tmp15, i32 0, i32 3 ; <i64*> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Di128-addsub.ll13 %tmp15 = add i128 %tmp12, %tmp5 ; <i128> [#uses=2]
14 %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
16 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
32 %tmp15 = sub i128 %tmp5, %tmp12 ; <i128> [#uses=2]
33 %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
35 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll13 %tmp15 = add i128 %tmp12, %tmp5 ; <i128> [#uses=2]
14 %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
16 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
32 %tmp15 = sub i128 %tmp5, %tmp12 ; <i128> [#uses=2]
33 %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
35 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Daddsub-i128.ll16 %tmp15 = add i128 %tmp12, %tmp5 ; <i128> [#uses=2]
17 %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
19 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
35 %tmp15 = sub i128 %tmp5, %tmp12 ; <i128> [#uses=2]
36 %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
38 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
/external/llvm/test/Analysis/ScalarEvolution/
Dpr25369.ll33 %tmp14 = phi i64 [ 0, %bb3 ], [ %tmp15, %bb13 ]
34 %tmp15 = add nuw nsw i64 %tmp14, 1
35 %tmp16 = trunc i64 %tmp15 to i32
70 %tmp14 = phi i64 [ 0, %bb3 ], [ %tmp15, %bb13 ]
71 %tmp15 = add nuw nsw i64 %tmp14, 1
72 %tmp16 = trunc i64 %tmp15 to i32
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Difcvt2.ll13 %tmp15 = add i32 %tmp13, %c
14 %tmp1821 = sub i32 %tmp15, %d
36 %tmp15 = add i32 %tmp13, %c
37 %tmp1821 = sub i32 %tmp15, %d
/external/llvm/test/CodeGen/ARM/
Difcvt2.ll13 %tmp15 = add i32 %tmp13, %c
14 %tmp1821 = sub i32 %tmp15, %d
36 %tmp15 = add i32 %tmp13, %c
37 %tmp1821 = sub i32 %tmp15, %d
/external/llvm/test/CodeGen/X86/
D2006-10-10-FindModifiedNodeSlotBug.ll15 %tmp15 = lshr i32 %tmp14, 31 ; <i32> [#uses=1]
16 %tmp15.upgrd.3 = trunc i32 %tmp15 to i8 ; <i8> [#uses=1]
17 %tmp16 = icmp ne i8 %tmp15.upgrd.3, 0 ; <i1> [#uses=1]
D2009-04-25-CoalescerBug.ll9 %tmp15 = load i32, i32* %tmp13 ; <i32> [#uses=2]
10 %bf.lo = lshr i32 %tmp15, 1 ; <i32> [#uses=1]
13 %bf.lo.cleared25 = and i32 %tmp15, 1 ; <i32> [#uses=1]
Dfp-stack.ll9 %tmp15 = load x86_fp80, x86_fp80* undef ; <x86_fp80> [#uses=2]
14 %cmp139 = fcmp ogt x86_fp80 %tmp15, %tmp6 ; <i1> [#uses=1]
15 %maxdiag.0 = select i1 %cmp139, x86_fp80 %tmp15, x86_fp80 %tmp6 ; <x86_fp80> [#uses=1]
Dshrink_vmul.ll39 %tmp15 = bitcast i32* %tmp14 to <2 x i32>*
40 store <2 x i32> %tmp13, <2 x i32>* %tmp15, align 4
75 %tmp15 = bitcast i32* %tmp14 to <4 x i32>*
76 store <4 x i32> %tmp13, <4 x i32>* %tmp15, align 4
114 %tmp15 = bitcast i32* %tmp14 to <8 x i32>*
115 store <8 x i32> %tmp13, <8 x i32>* %tmp15, align 4
163 %tmp15 = bitcast i32* %tmp14 to <16 x i32>*
164 store <16 x i32> %tmp13, <16 x i32>* %tmp15, align 4
198 %tmp15 = bitcast i32* %tmp14 to <2 x i32>*
199 store <2 x i32> %tmp13, <2 x i32>* %tmp15, align 4
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dsi-lower-control-flow-unreachable-block.ll16 %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
17 %tmp63 = icmp eq i32 %tmp15, 32
39 %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
40 %tmp63 = icmp eq i32 %tmp15, 32
Dllvm.AMDGPU.cube.ll25 %tmp15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp14)
26 %tmp16 = extractelement <4 x float> %tmp15, i32 0
27 %tmp17 = extractelement <4 x float> %tmp15, i32 1
28 %tmp18 = extractelement <4 x float> %tmp15, i32 2
29 %tmp19 = extractelement <4 x float> %tmp15, i32 3
/external/llvm/test/CodeGen/WebAssembly/
Dirreducible-cfg.ll38 %tmp15 = phi i32 [ undef, %bb3 ], [ %tmp7, %bb9 ]
39 %tmp16 = getelementptr double, double* %arg, i32 %tmp15
42 %tmp18 = add nsw i32 %tmp15, 1
85 %tmp15 = phi i32 [ undef, %bb3 ], [ %tmp7, %bb10 ]
86 %tmp16 = getelementptr double, double* %arg, i32 %tmp15
89 %tmp18 = add nsw i32 %tmp15, 1
/external/libjpeg-turbo/
Djidctint.c1466 JLONG tmp10, tmp11, tmp12, tmp13, tmp14, tmp15; in jpeg_idct_12x12() local
1529 tmp15 = MULTIPLY(tmp10 + z4, FIX(0.860918669)); /* c7 */ in jpeg_idct_12x12()
1530 tmp12 = tmp15 + MULTIPLY(tmp10, FIX(0.261052384)); /* c5-c7 */ in jpeg_idct_12x12()
1534 tmp13 += tmp15 - tmp11 + MULTIPLY(z4, FIX(1.586706681)); /* c1+c11 */ in jpeg_idct_12x12()
1535 tmp15 += tmp14 - MULTIPLY(z1, FIX(0.676326758)) - /* c7-c11 */ in jpeg_idct_12x12()
1556 wsptr[8*5] = (int) RIGHT_SHIFT(tmp25 + tmp15, CONST_BITS-PASS1_BITS); in jpeg_idct_12x12()
1557 wsptr[8*6] = (int) RIGHT_SHIFT(tmp25 - tmp15, CONST_BITS-PASS1_BITS); in jpeg_idct_12x12()
1610 tmp15 = MULTIPLY(tmp10 + z4, FIX(0.860918669)); /* c7 */ in jpeg_idct_12x12()
1611 tmp12 = tmp15 + MULTIPLY(tmp10, FIX(0.261052384)); /* c5-c7 */ in jpeg_idct_12x12()
1615 tmp13 += tmp15 - tmp11 + MULTIPLY(z4, FIX(1.586706681)); /* c1+c11 */ in jpeg_idct_12x12()
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Dintrapred16_dspr2.c17 int32_t tmp9, tmp10, tmp11, tmp12, tmp13, tmp14, tmp15, tmp16; in vpx_h_predictor_16x16_dspr2() local
154 [tmp13] "=&r"(tmp13), [tmp14] "=&r"(tmp14), [tmp15] "=&r"(tmp15), in vpx_h_predictor_16x16_dspr2()
/external/llvm/test/CodeGen/Hexagon/
Dsube.ll22 %tmp15 = sub i128 %tmp5, %tmp12
23 %tmp1617 = trunc i128 %tmp15 to i64
25 %tmp21 = lshr i128 %tmp15, 64
Dadde.ll27 %tmp15 = add i128 %tmp12, %tmp5
28 %tmp1617 = trunc i128 %tmp15 to i64
30 %tmp21 = lshr i128 %tmp15, 64

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