Searched refs:tmpSPVReg (Results 1 – 2 of 2) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 11788 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), in EmitLoweredSegAlloca() local
11805 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); in EmitLoweredSegAlloca()
11806 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg) in EmitLoweredSegAlloca()
11807 .addReg(tmpSPVReg).addReg(sizeVReg); in EmitLoweredSegAlloca()
11810 .addReg(tmpSPVReg); in EmitLoweredSegAlloca()
11816 .addReg(tmpSPVReg); in EmitLoweredSegAlloca()
11818 .addReg(tmpSPVReg); in EmitLoweredSegAlloca()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 23496 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), in EmitLoweredSegAlloca() local
23514 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); in EmitLoweredSegAlloca()
23516 .addReg(tmpSPVReg).addReg(sizeVReg); in EmitLoweredSegAlloca()
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