| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-umaxv.ll | 5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
10 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
33 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
54 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
75 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
[all …]
|
| D | arm64-neon-across.ll | 41 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)
43 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)
45 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)
53 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)
55 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)
185 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
187 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)
188 %0 = trunc i32 %umaxv.i to i8
194 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
196 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a)
[all …]
|
| D | arm64-vecCmpBr.ll | 58 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
66 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
82 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
89 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
105 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
112 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
128 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
135 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
195 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2
197 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2
|
| D | aarch64-minmaxv.ll | 78 ; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
100 ; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
119 ; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
135 ; CHECK-NOT: umaxv
324 ; CHECK: umaxv {{h[0-9]+}}, [[V0]]
349 ; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-across.s | 57 umaxv b0, v1.8b
58 umaxv b0, v1.16b
59 umaxv h0, v1.4h
60 umaxv h0, v1.8h
61 umaxv s0, v1.4s
|
| D | neon-diagnostics.s | 3775 umaxv s0, v1.2s
3797 umaxv d0, v1.2d define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2248 __ umaxv(b17, v30.V16B()); in GenerateTestSequenceNEON() local
2249 __ umaxv(b23, v12.V8B()); in GenerateTestSequenceNEON() local
2250 __ umaxv(h31, v15.V4H()); in GenerateTestSequenceNEON() local
2251 __ umaxv(h15, v25.V8H()); in GenerateTestSequenceNEON() local
2252 __ umaxv(s18, v21.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4410 DEFINE_TEST_NEON_ACROSS(umaxv, Basic)
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 1905 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b
1906 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b
1907 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h
1908 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h
1909 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s
|
| D | log-disasm-colour | 1905 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b
1906 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b
1907 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h
1908 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h
1909 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s
|
| D | log-all | 5113 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b
5115 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b
5117 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h
5119 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h
5121 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2217 void umaxv(const VRegister& vd, const VRegister& vn);
|
| D | simulator-aarch64.h | 2434 LogicVRegister umaxv(VectorFormat vform,
|
| D | macro-assembler-aarch64.h | 2323 V(umaxv, Umaxv) \
|
| D | simulator-aarch64.cc | 3721 umaxv(vf, rd, rn); in VisitNEONAcrossLanes()
|
| D | logic-aarch64.cc | 1622 LogicVRegister Simulator::umaxv(VectorFormat vform, in umaxv() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 3486 V(umaxv, NEON_UMAXV, true) \
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4200 void umaxv(const VRegister& vd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4128 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 315 aarch64_neon_umaxv, // llvm.aarch64.neon.umaxv
6373 "llvm.aarch64.neon.umaxv",
14313 1, // llvm.aarch64.neon.umaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 307 aarch64_neon_umaxv, // llvm.aarch64.neon.umaxv
6331 "llvm.aarch64.neon.umaxv",
14216 1, // llvm.aarch64.neon.umaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 315 aarch64_neon_umaxv, // llvm.aarch64.neon.umaxv
6373 "llvm.aarch64.neon.umaxv",
14313 1, // llvm.aarch64.neon.umaxv
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 315 aarch64_neon_umaxv, // llvm.aarch64.neon.umaxv
6373 "llvm.aarch64.neon.umaxv",
14313 1, // llvm.aarch64.neon.umaxv
|