| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 198 ;CHECK: ursqrte.2s
200 %tmp3 = call <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32> %tmp1)
206 ;CHECK: ursqrte.4s
208 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32> %tmp1)
212 declare <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32>) nounwind readnone
213 declare <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32>) nounwind readnone
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 676 ursqrte v6.4s, v8.4s
677 ursqrte v4.2s, v0.2s
|
| D | neon-diagnostics.s | 5947 ursqrte v0.16b, v31.16b
5948 ursqrte v2.8h, v4.8h
5949 ursqrte v1.8b, v9.8b
5950 ursqrte v13.4h, v21.4h
5951 ursqrte v1.2d, v9.2d
|
| D | arm64-advsimd.s | 605 ursqrte.2s v0, v0
655 ; CHECK: ursqrte.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x2e]
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1999 void ursqrte(const VRegister& vd, const VRegister& vn);
|
| D | simulator-aarch64.h | 2877 LogicVRegister ursqrte(VectorFormat vform,
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| D | macro-assembler-aarch64.h | 2328 V(ursqrte, Ursqrte) \
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| D | simulator-aarch64.cc | 3186 ursqrte(fpf, rd, rn); in VisitNEON2RegMisc()
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| D | logic-aarch64.cc | 4824 LogicVRegister Simulator::ursqrte(VectorFormat vform, in ursqrte() function in vixl::aarch64::Simulator
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| D | assembler-aarch64.cc | 3397 void Assembler::ursqrte(const VRegister& vd, const VRegister& vn) { in ursqrte() function in vixl::aarch64::Assembler
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2407 __ ursqrte(v20.V2S(), v16.V2S()); in GenerateTestSequenceNEON() local
2408 __ ursqrte(v28.V4S(), v8.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4359 DEFINE_TEST_NEON_2SAME_2S_4S(ursqrte, Basic) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 2064 0x~~~~~~~~~~~~~~~~ 2ea1ca14 ursqrte v20.2s, v16.2s
2065 0x~~~~~~~~~~~~~~~~ 6ea1c91c ursqrte v28.4s, v8.4s
|
| D | log-disasm-colour | 2064 0x~~~~~~~~~~~~~~~~ 2ea1ca14 ursqrte v20.2s, v16.2s
2065 0x~~~~~~~~~~~~~~~~ 6ea1c91c ursqrte v28.4s, v8.4s
|
| D | log-all | 5431 0x~~~~~~~~~~~~~~~~ 2ea1ca14 ursqrte v20.2s, v16.2s
5433 0x~~~~~~~~~~~~~~~~ 6ea1c91c ursqrte v28.4s, v8.4s
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4489 void ursqrte(const VRegister& vd,
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 504 # CHECK: ursqrte.2s v0, v0
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 28760 ursqrte v6.4s, v27.4s 6e368c61fa7a2d56e377a76471a733e2 bff3eb2bd48ec88fe61329d2eb55b3d1 940000…
28761 ursqrte v6.2s, v27.2s 1db9feff0e51bafc213da3e016175ed6 1e1e24f9ca7969dd1091a0e7dfda5845 000000…
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2898 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 330 aarch64_neon_ursqrte, // llvm.aarch64.neon.ursqrte
6388 "llvm.aarch64.neon.ursqrte",
14328 1, // llvm.aarch64.neon.ursqrte
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 322 aarch64_neon_ursqrte, // llvm.aarch64.neon.ursqrte
6346 "llvm.aarch64.neon.ursqrte",
14231 1, // llvm.aarch64.neon.ursqrte
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 330 aarch64_neon_ursqrte, // llvm.aarch64.neon.ursqrte
6388 "llvm.aarch64.neon.ursqrte",
14328 1, // llvm.aarch64.neon.ursqrte
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 330 aarch64_neon_ursqrte, // llvm.aarch64.neon.ursqrte
6388 "llvm.aarch64.neon.ursqrte",
14328 1, // llvm.aarch64.neon.ursqrte
|