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Searched refs:ursra (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s143 ursra v0.8b, v1.8b, #3
144 ursra v0.4h, v1.4h, #3
145 ursra v0.2s, v1.2s, #3
146 ursra v0.16b, v1.16b, #3
147 ursra v0.8h, v1.8h, #3
148 ursra v0.4s, v1.4s, #3
149 ursra v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s57 ursra d18, d10, #13
Darm64-advsimd.s1393 ursra d0, d0, #1 define
1442 ; CHECK: ursra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x7f]
1595 ursra.8b v0, v0, #1
1596 ursra.16b v0, v0, #2
1597 ursra.4h v0, v0, #3
1598 ursra.8h v0, v0, #4
1599 ursra.2s v0, v0, #5
1600 ursra.4s v0, v0, #6
1601 ursra.2d v0, v0, #7
1767 ; CHECK: ursra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x2f]
[all …]
Dneon-diagnostics.s1609 ursra v0.8b, v1.8h, #3
1610 ursra v0.4h, v1.4s, #3
1611 ursra v0.2s, v1.2d, #3
1612 ursra v0.16b, v1.16b, #9
1613 ursra v0.8h, v1.8h, #17
1614 ursra v0.4s, v1.4s, #33
1615 ursra v0.2d, v1.2d, #65
4983 ursra d18, d10, #99
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1846 # CHECK: ursra d0, d0, #0x3f
2170 # CHECK: ursra.8b v0, v0, #0x7
2171 # CHECK: ursra.16b v0, v0, #0x6
2172 # CHECK: ursra.4h v0, v0, #0xd
2173 # CHECK: ursra.8h v0, v0, #0xc
2174 # CHECK: ursra.2s v0, v0, #0x1b
2175 # CHECK: ursra.4s v0, v0, #0x1a
2176 # CHECK: ursra.2d v0, v0, #0x39
Dneon-instructions.txt846 # CHECK: ursra v0.8b, v1.8b, #3
847 # CHECK: ursra v0.4h, v1.4h, #3
848 # CHECK: ursra v0.2s, v1.2s, #3
849 # CHECK: ursra v0.16b, v1.16b, #3
850 # CHECK: ursra v0.8h, v1.8h, #3
851 # CHECK: ursra v0.4s, v1.4s, #3
852 # CHECK: ursra v0.2d, v1.2d, #3
1858 # CHECK: ursra d18, d10, #13
/external/llvm/test/CodeGen/AArch64/
Darm64-vshift.ll1375 ;CHECK: ursra.8b v0, {{v[0-9]+}}, #1
1385 ;CHECK: ursra.4h v0, {{v[0-9]+}}, #1
1395 ;CHECK: ursra.2s v0, {{v[0-9]+}}, #1
1405 ;CHECK: ursra.16b v0, {{v[0-9]+}}, #1
1415 ;CHECK: ursra.8h v0, {{v[0-9]+}}, #1
1425 ;CHECK: ursra.4s v0, {{v[0-9]+}}, #1
1435 ;CHECK: ursra.2d v0, {{v[0-9]+}}, #1
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28623 ursra d5, d28, #1 53b57c041e6f2038f0e51c6ce87ead3d c67d8f1b0845c18440c1148a5a5052ee 00000000000…
28624 ursra d5, d28, #32 833c3e696933f17d19c9aaccfa7d9eea ded005dc28fa3377b6be9001e037fad1 0000000000…
28625 ursra d5, d28, #64 bb48c208a4bff9a8e0d4bd2dbd41d542 9d4d3dedfce1c6f03797e120ad61228d 0000000000…
28647 ursra v6.2d, v27.2d, #1 e73670cb5ff6d914035227aa5d817429 f3d11afaf2d8dbdd22eaa3615cb797c9 611e…
28648 ursra v6.2d, v27.2d, #32 23b888bbe63dede832f065688aaaf32c 35eaded851428a37d37082b60f44566a 23b…
28649 ursra v6.2d, v27.2d, #64 5a87943573c47068d09fecd4f196f5bd 0a476e77ce63fff58dfe82f1130cef53 5a8…
28650 ursra v6.4s, v27.4s, #1 ec83f4186569c1733e401acff125d9bf d2c92bb8c81b9af6ad7602f2c8efc263 55e8…
28651 ursra v6.4s, v27.4s, #16 3a8c09461c0d40ebdbb15137ea37ff11 ee51747ba04abc1c95b662988fcc307c 3a8…
28652 ursra v6.4s, v27.4s, #32 a382339ef9904eae08d3f1ed3dacc793 bdbda9a0b5cfc545a59f02c5c785987d a38…
28653 ursra v6.2s, v27.2s, #1 8845d0ff5bd14a9d248559d149649224 9fed2b07678c13523b114357d0f85b45 0000…
[all …]
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2409 __ ursra(d27, d16, 45); in GenerateTestSequenceNEON() local
2410 __ ursra(v18.V16B(), v17.V16B(), 3); in GenerateTestSequenceNEON() local
2411 __ ursra(v26.V2D(), v28.V2D(), 58); in GenerateTestSequenceNEON() local
2412 __ ursra(v8.V2S(), v22.V2S(), 31); in GenerateTestSequenceNEON() local
2413 __ ursra(v31.V4H(), v4.V4H(), 7); in GenerateTestSequenceNEON() local
2414 __ ursra(v31.V4S(), v15.V4S(), 2); in GenerateTestSequenceNEON() local
2415 __ ursra(v3.V8B(), v1.V8B(), 5); in GenerateTestSequenceNEON() local
2416 __ ursra(v18.V8H(), v14.V8H(), 13); in GenerateTestSequenceNEON() local
Dtest-simulator-aarch64.cc4252 DEFINE_TEST_NEON_2OPIMM(ursra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4284 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(ursra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
/external/vixl/test/test-trace-reference/
Dlog-disasm2066 0x~~~~~~~~~~~~~~~~ 7f53361b ursra d27, d16, #45
2067 0x~~~~~~~~~~~~~~~~ 6f0d3632 ursra v18.16b, v17.16b, #3
2068 0x~~~~~~~~~~~~~~~~ 6f46379a ursra v26.2d, v28.2d, #58
2069 0x~~~~~~~~~~~~~~~~ 2f2136c8 ursra v8.2s, v22.2s, #31
2070 0x~~~~~~~~~~~~~~~~ 2f19349f ursra v31.4h, v4.4h, #7
2071 0x~~~~~~~~~~~~~~~~ 6f3e35ff ursra v31.4s, v15.4s, #2
2072 0x~~~~~~~~~~~~~~~~ 2f0b3423 ursra v3.8b, v1.8b, #5
2073 0x~~~~~~~~~~~~~~~~ 6f1335d2 ursra v18.8h, v14.8h, #13
Dlog-disasm-colour2066 0x~~~~~~~~~~~~~~~~ 7f53361b ursra d27, d16, #45
2067 0x~~~~~~~~~~~~~~~~ 6f0d3632 ursra v18.16b, v17.16b, #3
2068 0x~~~~~~~~~~~~~~~~ 6f46379a ursra v26.2d, v28.2d, #58
2069 0x~~~~~~~~~~~~~~~~ 2f2136c8 ursra v8.2s, v22.2s, #31
2070 0x~~~~~~~~~~~~~~~~ 2f19349f ursra v31.4h, v4.4h, #7
2071 0x~~~~~~~~~~~~~~~~ 6f3e35ff ursra v31.4s, v15.4s, #2
2072 0x~~~~~~~~~~~~~~~~ 2f0b3423 ursra v3.8b, v1.8b, #5
2073 0x~~~~~~~~~~~~~~~~ 6f1335d2 ursra v18.8h, v14.8h, #13
Dlog-all5435 0x~~~~~~~~~~~~~~~~ 7f53361b ursra d27, d16, #45
5437 0x~~~~~~~~~~~~~~~~ 6f0d3632 ursra v18.16b, v17.16b, #3
5439 0x~~~~~~~~~~~~~~~~ 6f46379a ursra v26.2d, v28.2d, #58
5441 0x~~~~~~~~~~~~~~~~ 2f2136c8 ursra v8.2s, v22.2s, #31
5443 0x~~~~~~~~~~~~~~~~ 2f19349f ursra v31.4h, v4.4h, #7
5445 0x~~~~~~~~~~~~~~~~ 6f3e35ff ursra v31.4s, v15.4s, #2
5447 0x~~~~~~~~~~~~~~~~ 2f0b3423 ursra v3.8b, v1.8b, #5
5449 0x~~~~~~~~~~~~~~~~ 6f1335d2 ursra v18.8h, v14.8h, #13
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc4897 ursra(vf, rd, rn, right_shift); in VisitNEONScalarShiftImmediate()
5024 ursra(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
Dassembler-aarch64.h2268 void ursra(const VRegister& vd, const VRegister& vn, int shift);
Dsimulator-aarch64.h2528 LogicVRegister ursra(VectorFormat vform,
Dmacro-assembler-aarch64.h2435 V(ursra, Ursra) \
Dlogic-aarch64.cc1841 LogicVRegister Simulator::ursra(VectorFormat vform, in ursra() function in vixl::aarch64::Simulator
Dassembler-aarch64.cc3749 void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) { in ursra() function in vixl::aarch64::Assembler
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md4497 void ursra(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4741 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4797 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",