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Searched refs:v128i16 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h85 v128i16 = 37, //128 x i16 enumerator
279 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
341 case v128i16: return i16; in getVectorElementType()
379 case v128i16: return 128; in getVectorNumElements()
509 case v128i16: in getSizeInBits()
621 if (NumElements == 128) return MVT::v128i16; in getVectorVT()
DValueTypes.td62 def v128i16: ValueType<2048,37>; //128 x i16 vector value
/external/llvm/lib/IR/
DValueTypes.cpp169 case MVT::v128i16: return "v128i16"; in getEVTString()
247 case MVT::v128i16: return VectorType::get(Type::getInt16Ty(Context), 128); in getTypeForEVT()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
424 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 || in RetCC_Hexagon()
547 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1141 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { in LowerFormalArguments()
1770 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
2005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); in HexagonTargetLowering()
2897 case MVT::v128i16: in getRegForInlineAsmConstraint()
3033 case MVT::v128i16: in allowsMisalignedMemoryAccesses()
3072 case MVT::v128i16: in findRepresentativeClass()
DHexagonRegisterInfo.td238 [v256i8,v128i16,v64i32,v32i64], 2048,
DHexagonInstrInfoV60.td799 defm : STrivv_pats <v64i16, v128i16>;
874 defm : LDrivv_pats <v64i16, v128i16>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp97 case MVT::v128i16: return "MVT::v128i16"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td195 def llvm_v128i16_ty : LLVMType<v128i16>; //128 x i16