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Searched refs:v16i64 (Results 1 – 16 of 16) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h99 v16i64 = 49, // 16 x i64 enumerator
274 SimpleTy == MVT::v16i64); in is1024BitVector()
353 case v16i64: in getVectorElementType()
393 case v16i64: in getVectorNumElements()
507 case v16i64: return 1024; in getSizeInBits()
637 if (NumElements == 16) return MVT::v16i64; in getVectorVT()
DValueTypes.td76 def v16i64 : ValueType<1024,49>; // 16 x i64 vector value
/external/llvm/lib/IR/
DValueTypes.cpp181 case MVT::v16i64: return "v16i64"; in getEVTString()
259 case MVT::v16i64: return VectorType::get(Type::getInt64Ty(Context), 16); in getTypeForEVT()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
419 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || in RetCC_Hexagon()
545 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
898 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 || in getIndexedAddressParts()
1125 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1133 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1762 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering()
1768 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering()
[all …]
DHexagonRegisterInfo.td230 [v128i8, v64i16, v32i32, v16i64], 1024,
234 [v128i8, v64i16, v32i32, v16i64], 1024,
DHexagonIntrinsicsV60.td139 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
140 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
159 def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
160 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
DHexagonISelDAGToDAG.cpp288 case MVT::v16i64: in SelectIndexedLoad()
576 case MVT::v16i64: in SelectIndexedStore()
DHexagonInstrInfoV60.td801 defm : STrivv_pats <v16i64, v32i64>;
851 defm : vS32b_ai_pats <v8i64, v16i64>;
876 defm : LDrivv_pats <v16i64, v32i64>;
916 defm : vL32b_ai_pats <v8i64, v16i64>;
DHexagonInstrInfo.cpp2632 if (VT == MVT::v32i32 || VT == MVT::v16i64 || in isValidAutoIncImm()
/external/llvm/test/CodeGen/AMDGPU/
Dctpop64.ll8 declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp109 case MVT::v16i64: return "MVT::v16i64"; in getEnumName()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp451 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp303 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } in getCmpSelInstrCost()
/external/llvm/test/CodeGen/X86/
Dmasked_gather_scatter.ll1701 …%res = call <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*> %ptrs, i32 4, <16 x i1> %mask, <16 x…
1704 declare <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*> %ptrs, i32, <16 x i1> %mask, <16 x i64> %…
1937 call void @llvm.masked.scatter.v16i64(<16 x i64> %src0, <16 x i64*> %ptrs, i32 4, <16 x i1> %mask)
1940 declare void @llvm.masked.scatter.v16i64(<16 x i64> %src0, <16 x i64*> %ptrs, i32, <16 x i1> %mask)
Dmasked_memop.ll1698 …call void @llvm.masked.store.v16i64.p0v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32 4, <16 x i1>…
1701 declare void @llvm.masked.store.v16i64.p0v16i64(<16 x i64> %src0, <16 x i64>* %ptrs, i32, <16 x i1>…
1894 …%res = call <16 x i64> @llvm.masked.load.v16i64.p0v16i64(<16 x i64>* %ptrs, i32 4, <16 x i1> %mask…
1897 declare <16 x i64> @llvm.masked.load.v16i64.p0v16i64(<16 x i64>* %ptrs, i32, <16 x i1> %mask, <16 x…
/external/llvm/include/llvm/IR/
DIntrinsics.td209 def llvm_v16i64_ty : LLVMType<v16i64>; // 16 x i64