Searched refs:v64i16 (Results 1 – 12 of 12) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 84 v64i16 = 36, // 64 x i16 enumerator
273 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
340 case v64i16: in getVectorElementType()
382 case v64i16: in getVectorNumElements()
505 case v64i16: in getSizeInBits()
620 if (NumElements == 64) return MVT::v64i16; in getVectorVT()
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| D | ValueTypes.td | 61 def v64i16 : ValueType<1024,36>; // 64 x i16 vector value
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | bitconvert-vector.ll | 3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
149 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
150 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
832 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
833 (v64i16 (V6_vpackwh_sat_128B
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| D | HexagonISelLowering.cpp | 203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
418 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || in RetCC_Hexagon()
545 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
899 VT == MVT::v64i16 || VT == MVT::v128i8); in getIndexedAddressParts()
1126 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { in LowerFormalArguments()
1134 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { in LowerFormalArguments()
1760 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering()
1766 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering()
[all …]
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| D | HexagonRegisterInfo.td | 230 [v128i8, v64i16, v32i32, v16i64], 1024,
234 [v128i8, v64i16, v32i32, v16i64], 1024,
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| D | HexagonISelDAGToDAG.cpp | 286 case MVT::v64i16: in SelectIndexedLoad()
574 case MVT::v64i16: in SelectIndexedStore()
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| D | HexagonInstrInfoV60.td | 799 defm : STrivv_pats <v64i16, v128i16>;
849 defm : vS32b_ai_pats <v32i16, v64i16>;
874 defm : LDrivv_pats <v64i16, v128i16>;
914 defm : vL32b_ai_pats <v32i16, v64i16>;
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| D | HexagonInstrInfo.cpp | 2633 VT == MVT::v64i16 || VT == MVT::v128i8) { in isValidAutoIncImm()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 168 case MVT::v64i16: return "v64i16"; in getEVTString()
246 case MVT::v64i16: return VectorType::get(Type::getInt16Ty(Context), 64); in getTypeForEVT()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 96 case MVT::v64i16: return "MVT::v64i16"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 194 def llvm_v64i16_ty : LLVMType<v64i16>; // 64 x i16
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