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Searched refs:v_mov_b32_e32 (Results 1 – 25 of 140) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dfcanonicalize.ll26 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
44 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
53 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
62 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x41800000{{$}}
71 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
80 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fffff{{$}}
89 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
98 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x807fffff{{$}}
107 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}}
116 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}}
[all …]
Dbitreverse-inline-immediates.ll8 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0{{$}}
16 ; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
17 ; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}}
25 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -1{{$}}
33 ; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
34 ; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}}
50 ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
67 ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
76 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xf7ffffff{{$}}
84 ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
[all …]
Daddrspacecast.ll11 ; HSA-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
12 ; HSA-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
17 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
34 ; HSA-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
35 ; HSA-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
40 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
54 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
55 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
56 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
67 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
[all …]
Dcaptured-frame-index.ll5 ; GCN: v_mov_b32_e32 [[ZERO1:v[0-9]+]], 0{{$}}
7 ; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}}
8 ; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
19 ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
25 ; GCN-DAG: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
28 ; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 4{{$}}
42 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x4d2{{$}}
43 ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
57 ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
58 ; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 32{{$}}
[all …]
Dllvm.amdgcn.atomic.dec.ll15 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
24 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
35 ; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
36 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
44 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
53 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
62 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
79 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
88 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
102 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
[all …]
Dllvm.amdgcn.atomic.inc.ll15 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
24 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
35 ; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
36 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
44 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
53 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
62 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
79 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
88 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
102 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
[all …]
Dret.ll7 ; GCN: v_mov_b32_e32 v1, v0
23 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
24 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
25 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
26 ; GCN-DAG: v_mov_b32_e32 v3, -1.0
39 ; GCN-NOT: v_mov_b32_e32 v0
40 ; GCN-NOT: v_mov_b32_e32 v1
41 ; GCN-NOT: v_mov_b32_e32 v2
42 ; GCN: v_mov_b32_e32 v3, v4
43 ; GCN: v_mov_b32_e32 v4, v6
[all …]
Datomic_cmp_swap_local.ll10 ; GCN: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
11 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
12 ; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
28 ; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
29 ; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
30 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
31 ; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
32 ; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
63 ; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
64 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
[all …]
Dread_register.ll8 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], m0
18 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo
19 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi
28 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], flat_scratch_lo
29 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], flat_scratch_hi
38 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_lo
47 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_hi
56 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
65 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
Dglobal-variable-relocs.ll19 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]]
20 ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]]
33 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]]
34 ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]]
50 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
51 ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
67 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
68 ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
84 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
85 ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
[all …]
Dbuild_vector.ll10 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
11 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
26 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
27 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
28 ; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
29 ; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
Dshift-and-i128-ubfe.ll7 ; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
8 ; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}}
9 ; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
29 ; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
30 ; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
31 ; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
51 ; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
52 ; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}}
53 ; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}}
73 ; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
[all …]
Dimm.ll6 ; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], 5
16 ; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], 5
25 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
42 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
58 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
66 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
74 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
82 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
90 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
98 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
[all …]
Duse-sgpr-multiple-times.ll35 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
53 ; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
75 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
89 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
131 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
142 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
154 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
170 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
182 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
198 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
[all …]
Dgep-address-space.ll7 ; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
32 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
33 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
34 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
35 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
58 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
59 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
Dllvm.amdgcn.workgroup.id.ll24 ; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s2{{$}}
25 ; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s6{{$}}
52 ; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
53 ; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
88 ; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
89 ; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
Duniform-cfg.ll6 ; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
10 ; SI: v_mov_b32_e32 [[STORE_VAL]], 1
36 ; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
40 ; SI: v_mov_b32_e32 [[STORE_VAL]], 1
63 ; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
67 ; SI: v_mov_b32_e32 [[STORE_VAL]], 1
93 ; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
97 ; SI: v_mov_b32_e32 [[STORE_VAL]], 1
173 ; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
178 ; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
[all …]
Damdgpu.work-item-intrinsics.deprecated.ll10 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
25 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
40 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
55 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
70 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
85 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
100 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
115 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
130 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
145 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
[all …]
Dllvm.r600.read.local.size.ll15 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
30 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
45 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
59 ; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
78 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
98 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
120 ; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
121 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
139 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
154 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
[all …]
Dllvm.AMDGPU.bfe.i32.ll88 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
183 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
207 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
219 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
231 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
243 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
255 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0xffffff80
267 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
279 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
[all …]
D32-bit-local-address-space.ll25 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
36 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
49 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
84 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
112 ; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
121 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
122 ; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
133 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
Dzext-i64-bit-operand.ll8 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
12 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
28 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
32 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
Dinsert_vector_elt.ll14 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
15 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
16 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
17 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
18 ; GCN-DAG: v_mov_b32_e32 [[CONSTREG:v[0-9]+]], 0x40a00000
19 ; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]]
86 ; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
96 ; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
107 ; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
148 ; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 5
[all …]
Dshift-and-i64-ubfe.ll9 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
26 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
42 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
58 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
74 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
90 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
106 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
122 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
138 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
156 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dmov.txt3 # CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e]
6 # CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e]
9 # CHECK: v_mov_b32_e32 v15, s100 ; encoding: [0x64,0x02,0x1e,0x7e]
12 # CHECK: v_mov_b32_e32 v90, flat_scratch_lo ; encoding: [0x66,0x02,0xb4,0x7e]
15 # CHECK: v_mov_b32_e32 v150, vcc_lo ; encoding: [0x6a,0x02,0x2c,0x7f]
18 # CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
21 # CHECK: v_mov_b32_e32 v222, m0 ; encoding: [0x7c,0x02,0xbc,0x7f]
24 # CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]

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