Searched refs:v_readfirstlane_b32 (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | missing-store.ll | 11 ; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
12 ; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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| D | si-triv-disjoint-mem-access.ll | 74 ; CI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
75 ; CI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
96 ; CI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
97 ; CI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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| D | indirect-addressing-si.ll | 84 ; CHECK: v_readfirstlane_b32
170 ; CHECK: v_readfirstlane_b32
185 ; CHECK: v_readfirstlane_b32
213 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
226 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
269 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
283 ; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]]
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| D | si-spill-sgpr-stack.ll | 8 ; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
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| D | salu-to-valu.ll | 58 ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
59 ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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| /external/llvm/test/MC/AMDGPU/ |
| D | trap.s | 138 v_readfirstlane_b32 ttmp8, v1 label
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| D | vop1.s | 38 v_readfirstlane_b32 s1, v2 label
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | trap_vi.txt | 105 # VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
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| D | vop1_vi.txt | 18 # VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1224 "v_readfirstlane_b32 $vdst, $src0",
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