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Searched refs:val1 (Results 1 – 25 of 357) sorted by relevance

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/external/libcxx/test/libcxx/atomics/
Ddiagnose_invalid_memory_order.fail.cpp22 int val1 = 1; ((void)val1); in main() local
74 …x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_release); // expe… in main()
75 …x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acq_rel); // expe… in main()
76 …vx.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_release); // exp… in main()
77 …vx.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acq_rel); // exp… in main()
79 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_relaxed); in main()
80 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_consume); in main()
81 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acquire); in main()
82 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_seq_cst); in main()
85 x.compare_exchange_weak(val1, val2, std::memory_order_release); in main()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dicmp16.ll16 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
17 ; $3 = %arg1, $4 = %val1, $5 = %val2
29 define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
32 %B = select i1 %A, i16 %val1, i16 %val2
36 define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
42 define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
45 %B = select i1 %A, i16 %val1, i16 %val2
49 define i16 @icmp_eq_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
52 %B = select i1 %A, i16 %val1, i16 %val2
56 define i16 @icmp_eq_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
[all …]
Dicmp32.ll16 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
17 ; $3 = %arg1, $4 = %val1, $5 = %val2
29 define i32 @icmp_eq_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
32 %B = select i1 %A, i32 %val1, i32 %val2
36 define i1 @icmp_eq_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
42 define i32 @icmp_eq_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
45 %B = select i1 %A, i32 %val1, i32 %val2
49 define i32 @icmp_eq_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
52 %B = select i1 %A, i32 %val1, i32 %val2
56 define i32 @icmp_eq_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
[all …]
Dicmp8.ll15 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
16 ; $3 = %arg1, $4 = %val1, $5 = %val2
28 define i8 @icmp_eq_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
31 %B = select i1 %A, i8 %val1, i8 %val2
35 define i1 @icmp_eq_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
41 define i8 @icmp_eq_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
44 %B = select i1 %A, i8 %val1, i8 %val2
48 define i8 @icmp_eq_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
51 %B = select i1 %A, i8 %val1, i8 %val2
55 define i8 @icmp_eq_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
[all …]
Dicmp64.ll14 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
15 ; $3 = %arg1, $4 = %val1, $5 = %val2
18 define i64 @icmp_eq_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
21 %B = select i1 %A, i64 %val1, i64 %val2
25 define i1 @icmp_eq_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
31 define i64 @icmp_ne_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
34 %B = select i1 %A, i64 %val1, i64 %val2
38 define i1 @icmp_ne_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
44 define i64 @icmp_ugt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
47 %B = select i1 %A, i64 %val1, i64 %val2
[all …]
/external/llvm/test/CodeGen/ARM/
Dvsel.ll7 %val1 = select i1 %tst1, float %a, float %b
8 store float %val1, float* @varfloat
16 %val1 = select i1 %tst1, double %a, double %b
17 store double %val1, double* @vardouble
25 %val1 = select i1 %tst1, float %a, float %b
26 store float %val1, float* @varfloat
34 %val1 = select i1 %tst1, double %a, double %b
35 store double %val1, double* @vardouble
43 %val1 = select i1 %tst1, float %a, float %b
44 store float %val1, float* @varfloat
[all …]
/external/valgrind/none/tests/s390x/
Dclgrj.c30 register uint64_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register uint64_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register uint64_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register uint64_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register uint64_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dcrj.c30 register int32_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register int32_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register int32_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register int32_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register int32_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dclrj.c30 register uint32_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register uint32_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register uint32_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register uint32_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register uint32_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dcgrj.c30 register int64_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register int64_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register int64_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register int64_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register int64_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-max-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val1, %val2
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val1, %val2
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val1, %val2
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-min-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val2, %val1
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val2, %val1
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val2, %val1
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val2, %val1
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val2, %val1
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val2, %val1
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-max-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val1, %val2
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val1, %val2
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val1, %val2
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val2, %val1
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val2, %val1
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val2, %val1
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-min-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val2, %val1
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val2, %val1
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val2, %val1
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-max-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val1, %val2
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val1, %val2
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val1, %val2
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-max-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val1, %val2
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val1, %val2
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val1, %val2
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-cmp-02.ll6 define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp eq <8 x i16> %val1, %val2
16 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
21 %cmp = icmp ne <8 x i16> %val1, %val2
27 define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
31 %cmp = icmp sgt <8 x i16> %val1, %val2
37 define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
42 %cmp = icmp sge <8 x i16> %val1, %val2
48 define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
53 %cmp = icmp sle <8 x i16> %val1, %val2
[all …]
Dcall-04.ll12 define void @f1(i32 %val1, i32 %val2) {
17 %cond = icmp slt i32 %val1, %val2;
30 define void @f2(i32 %val1, i32 %val2) {
35 %cond = icmp slt i32 %val1, %val2;
48 define void @f3(i32 %val1, i32 %val2) {
53 %cond = icmp slt i32 %val1, %val2;
66 define void @f4(i32 %val1, i32 %val2) {
71 %cond = icmp ult i32 %val1, %val2;
84 define void @f5(i64 %val1, i64 %val2) {
89 %cond = icmp slt i64 %val1, %val2;
[all …]
Dvec-cmp-01.ll6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp eq <16 x i8> %val1, %val2
16 define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
21 %cmp = icmp ne <16 x i8> %val1, %val2
27 define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
31 %cmp = icmp sgt <16 x i8> %val1, %val2
37 define <16 x i8> @f4(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
42 %cmp = icmp sge <16 x i8> %val1, %val2
48 define <16 x i8> @f5(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
53 %cmp = icmp sle <16 x i8> %val1, %val2
[all …]
Dvec-cmp-04.ll6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp eq <2 x i64> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
21 %cmp = icmp ne <2 x i64> %val1, %val2
27 define <2 x i64> @f3(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
31 %cmp = icmp sgt <2 x i64> %val1, %val2
37 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
42 %cmp = icmp sge <2 x i64> %val1, %val2
48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
53 %cmp = icmp sle <2 x i64> %val1, %val2
[all …]
/external/llvm/test/CodeGen/AArch64/
Dlogical_shifted_reg.ll11 %val1 = load i32, i32* @var1_32
17 %and_noshift = and i32 %val1, %val2
20 %bic_noshift = and i32 %neg_val2, %val1
24 %or_noshift = or i32 %val1, %val2
27 %orn_noshift = or i32 %neg_val2, %val1
31 %xor_noshift = xor i32 %val1, %val2
34 %xorn_noshift = xor i32 %neg_val2, %val1
42 %and_lsl31 = and i32 %val1, %operand_lsl31
45 %bic_lsl31 = and i32 %val1, %neg_operand_lsl31
49 %or_lsl31 = or i32 %val1, %operand_lsl31
[all …]
/external/elfutils/libdwfl/
Dframe_unwind.c170 Dwarf_Addr val1, val2; in expr_eval() local
218 if (! state_get_reg (state, op->atom - DW_OP_reg0, &val1) in expr_eval()
219 || ! push (val1)) in expr_eval()
226 if (! state_get_reg (state, op->number, &val1) || ! push (val1)) in expr_eval()
233 if (! state_get_reg (state, op->atom - DW_OP_breg0, &val1)) in expr_eval()
238 val1 += op->number; in expr_eval()
239 if (! push (val1)) in expr_eval()
246 if (! state_get_reg (state, op->number, &val1)) in expr_eval()
251 val1 += op->number2; in expr_eval()
252 if (! push (val1)) in expr_eval()
[all …]
/external/swiftshader/third_party/subzero/crosstest/
Dtest_select.h17 v4f32 select(v4si32 cond, v4f32 val1, v4f32 val2);
18 v4si32 select(v4si32 cond, v4si32 val1, v4si32 val2);
19 v4ui32 select(v4si32 cond, v4ui32 val1, v4ui32 val2);
20 v8si16 select(v8si16 cond, v8si16 val1, v8si16 val2);
21 v8ui16 select(v8si16 cond, v8ui16 val1, v8ui16 val2);
22 v16si8 select(v16si8 cond, v16si8 val1, v16si8 val2);
23 v16ui8 select(v16si8 cond, v16ui8 val1, v16ui8 val2);
24 v4si32 select_i1(v4si32 cond, v4si32 val1, v4si32 val2);
25 v8si16 select_i1(v8si16 cond, v8si16 val1, v8si16 val2);
26 v16si8 select_i1(v16si8 cond, v16si8 val1, v16si8 val2);

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