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Searched refs:virtReg2Index (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/WebAssembly/
DWebAssemblyMachineFunctionInfo.h63 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size()) in stackifyVReg()
64 VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1); in stackifyVReg()
65 VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg)); in stackifyVReg()
68 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size()) in isVRegStackified()
70 return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg)); in isVRegStackified()
76 assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size()); in setWAReg()
77 WARegs[TargetRegisterInfo::virtReg2Index(VReg)] = WAReg; in setWAReg()
80 assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size()); in getWAReg()
81 return WARegs[TargetRegisterInfo::virtReg2Index(Reg)]; in getWAReg()
DWebAssemblyRegColoring.cpp161 << TargetRegisterInfo::virtReg2Index(LI->reg) << " to vreg" in runOnMachineFunction()
162 << TargetRegisterInfo::virtReg2Index(New) << "\n"); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp209 unsigned MORegIdx = TargetRegisterInfo::virtReg2Index(MOReg); in addUsedLanesOnOperand()
237 TargetRegisterInfo::virtReg2Index(MI.getOperand(0).getReg())]); in transferUsedLanes()
294 unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg); in transferDefinedLanesStep()
366 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); in determineInitialDefinedLanes()
479 unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg); in isUndefInput()
547 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); in runOnce()
DTargetRegisterInfo.cpp53 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); in PrintReg()
93 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); in PrintVRegOrUnit()
DRegAllocFast.cpp80 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
185 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
188 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
DMIRPrinter.cpp155 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); in printReg()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h287 static unsigned virtReg2Index(unsigned Reg) { in virtReg2Index() function
684 return TargetRegisterInfo::virtReg2Index(Reg); in operator()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetRegisterInfo.cpp38 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); in print()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DVirtRegMap.h450 ImplicitDefed.set(TargetRegisterInfo::virtReg2Index(VirtReg)); in setIsImplicitlyDefined()
455 return ImplicitDefed[TargetRegisterInfo::virtReg2Index(VirtReg)]; in isImplicitlyDefined()
DTwoAddressInstructionPass.cpp1186 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); in runOnMachineFunction()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h329 static unsigned virtReg2Index(unsigned Reg) { in virtReg2Index() function
1087 return TargetRegisterInfo::virtReg2Index(Reg); in operator()
/external/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h44 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
DRegisterPressure.h263 return TargetRegisterInfo::virtReg2Index(Reg) + NumRegUnits;
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp150 return TargetRegisterInfo::virtReg2Index(v); in v2x()
252 unsigned RInd = TargetRegisterInfo::virtReg2Index(VR); in lookup()
1568 unsigned Idx = TargetRegisterInfo::virtReg2Index(I->first); in runOnMachineFunction()
DBitTracker.cpp80 OS << 'v' << TargetRegisterInfo::virtReg2Index(PV.R); in operator <<()
DHexagonSplitDouble.cpp246 unsigned u = TargetRegisterInfo::virtReg2Index(T); in partitionRegisters()
DHexagonBitSimplify.cpp108 return TargetRegisterInfo::virtReg2Index(v); in v2x()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp548 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); in runOnMachineFunction()