| /external/llvm/test/CodeGen/ARM/ |
| D | fnmscs.ll | 28 ; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
32 ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
49 ; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
53 ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
70 ; A8U: vnmul.f64 d
74 ; A8: vnmul.f64 d
91 ; A8U: vnmul.f64 d
95 ; A8: vnmul.f64 d
|
| D | fnmuls.ll | 7 ; CHECK: vnmul.f32 s0, s0, s1
15 ; CHECK: vnmul.f32 s0, s0, s1
|
| D | fnmul.ll | 15 ; CHECK: vnmul.f64
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | fnmscs.ll | 15 ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
32 ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
49 ; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
66 ; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
|
| D | fnmuls.ll | 7 ; CHECK: vnmul.f32 s0, s0, s1
15 ; CHECK: vnmul.f32 s0, s0, s1
|
| D | fnmul.ll | 1 ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep vnmul.f64
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | simple-fp-encoding.s | 27 @ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
28 vnmul.f64 d16, d17, d16
30 @ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
31 vnmul.f32 s0, s1, s0
|
| /external/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 35 vnmul.f64 d16, d17, d16
36 vnmul.f32 s0, s1, s0
38 @ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
39 @ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
|
| D | fullfp16.s | 20 vnmul.f16 s0, s1, s0
21 @ ARM: vnmul.f16 s0, s1, s0 @ encoding: [0xc0,0x09,0x20,0xee]
22 @ THUMB: vnmul.f16 s0, s1, s0 @ encoding: [0x20,0xee,0xc0,0x09]
|
| D | single-precision-fp.s | 9 vnmul.f64 d8, d9, d10
19 @ CHECK-ERRORS-NEXT: vnmul.f64 d8, d9, d10
|
| D | fullfp16-neg.s | 16 vnmul.f16 s0, s1, s0
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 28 # CHECK: vnmul.f64 d16, d17, d16
31 # CHECK: vnmul.f32 s0, s1, s0
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 28 # CHECK: vnmul.f64 d16, d17, d16
31 # CHECK: vnmul.f32 s0, s1, s0
|
| D | fullfp16-arm.txt | 15 # CHECK: vnmul.f16 s0, s1, s0
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| D | fullfp16-thumb.txt | 15 # CHECK: vnmul.f16 s0, s1, s0
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 254 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
259 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 4996 void vnmul(
4998 void vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vnmul() function
4999 vnmul(al, dt, rd, rn, rm); in vnmul()
5002 void vnmul(
5004 void vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vnmul() function
5005 vnmul(al, dt, rd, rn, rm); in vnmul()
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| D | disasm-aarch32.h | 1971 void vnmul(
1974 void vnmul(
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| D | assembler-aarch32.cc | 20600 void Assembler::vnmul( in vnmul() function in vixl::aarch32::Assembler
20620 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm); in vnmul()
20623 void Assembler::vnmul( in vnmul() function in vixl::aarch32::Assembler
20643 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm); in vnmul()
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| D | disasm-aarch32.cc | 5552 void Disassembler::vnmul( in vnmul() function in vixl::aarch32::Disassembler
5563 void Disassembler::vnmul( in vnmul() function in vixl::aarch32::Disassembler
23528 vnmul(CurrentCond(), in DecodeT32()
23554 vnmul(CurrentCond(), in DecodeT32()
66185 vnmul(condition, in DecodeA32()
66221 vnmul(condition, in DecodeA32()
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| D | macro-assembler-aarch32.h | 8284 vnmul(cond, dt, rd, rn, rm); in Vnmul()
8299 vnmul(cond, dt, rd, rn, rm); in Vnmul()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 421 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
426 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
435 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
|