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Searched refs:vrev16 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/ARM/
Dneont2-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01]
26 vrev16.8 q8, q8
Dneon-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3]
26 vrev16.8 q8, q8
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3]
26 vrev16.8 q8, q8
Dneont2-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01]
26 vrev16.8 q8, q8
/external/llvm/test/CodeGen/ARM/
Dbig-endian-neon-extend.ll6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
36 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
65 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
Dpopcnt.ll23 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
35 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
47 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
62 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
Dbig-endian-neon-trunc-store.ll18 ; CHECK: vrev16.8 [[REG]], [[REG]]
Dvrev.ll101 ;CHECK: vrev16.8
109 ;CHECK: vrev16.8
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrev.ll101 ;CHECK: vrev16.8
109 ;CHECK: vrev16.8
/external/vixl/src/aarch32/
Dassembler-aarch32.h5417 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
5418 void vrev16(DataType dt, DRegister rd, DRegister rm) { in vrev16() function
5419 vrev16(al, dt, rd, rm); in vrev16()
5422 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
5423 void vrev16(DataType dt, QRegister rd, QRegister rm) { in vrev16() function
5424 vrev16(al, dt, rd, rm); in vrev16()
Ddisasm-aarch32.h2182 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
2184 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
Dassembler-aarch32.cc22683 void Assembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Assembler
22710 Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm); in vrev16()
22713 void Assembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Assembler
22740 Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm); in vrev16()
Ddisasm-aarch32.cc6124 void Disassembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Disassembler
6133 void Disassembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Disassembler
26658 vrev16(CurrentCond(), in DecodeT32()
26685 vrev16(CurrentCond(), in DecodeT32()
41140 vrev16(al, dt, DRegister(rd), DRegister(rm)); in DecodeA32()
41162 vrev16(al, dt, QRegister(rd), QRegister(rm)); in DecodeA32()
Dmacro-assembler-aarch32.h9187 vrev16(cond, dt, rd, rm); in Vrev16()
9200 vrev16(cond, dt, rd, rm); in Vrev16()
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt868 # CHECK: vrev16.8 d16, d16
870 # CHECK: vrev16.8 q8, q8
Dneon.txt977 # CHECK: vrev16.8 d16, d16
979 # CHECK: vrev16.8 q8, q8
/external/v8/src/arm/
Dassembler-arm.h1409 void vrev16(NeonSize size, const QwNeonRegister dst,
Dassembler-arm.cc4634 void Assembler::vrev16(NeonSize size, const QwNeonRegister dst, in vrev16() function in v8::internal::Assembler
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt868 # CHECK: vrev16.8 d16, d16
870 # CHECK: vrev16.8 q8, q8
Dneon.txt977 # CHECK: vrev16.8 d16, d16
979 # CHECK: vrev16.8 q8, q8
/external/clang/include/clang/Basic/
Darm_neon.td785 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td4738 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4739 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td6319 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
6320 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;