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Searched refs:vsli (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/test/MC/ARM/
Dneon-shiftaccum-encoding.s142 vsli.8 d11, d12, #7
143 vsli.16 d12, d13, #15
144 vsli.32 d13, d14, #31
145 vsli.64 d14, d15, #63
146 vsli.8 q1, q8, #7
147 vsli.16 q2, q7, #15
148 vsli.32 q3, q4, #31
149 vsli.64 q4, q5, #63
160 vsli.8 d12, #7
161 vsli.16 d13, #15
[all …]
Dneont2-shiftaccum-encoding.s145 vsli.8 d11, d12, #7
146 vsli.16 d12, d13, #15
147 vsli.32 d13, d14, #31
148 vsli.64 d14, d15, #63
149 vsli.8 q1, q8, #7
150 vsli.16 q2, q7, #15
151 vsli.32 q3, q4, #31
152 vsli.64 q4, q5, #63
163 vsli.8 d12, #7
164 vsli.16 d13, #15
[all …]
Dneon-shift-encoding.s217 vsli.8 d16, d6, #7
218 vsli.16 d26, d18, #15
219 vsli.32 d11, d10, #31
220 vsli.64 d12, d19, #63
221 vsli.8 q1, q8, #7
222 vsli.16 q2, q7, #15
223 vsli.32 q3, q6, #31
224 vsli.64 q4, q5, #63
226 vsli.8 d16, #7
227 vsli.16 d15, #15
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-shiftaccum-encoding.s69 @ CHECK: vsli.8 d17, d16, #7 @ encoding: [0xcf,0xff,0x30,0x15]
70 vsli.8 d17, d16, #7
71 @ CHECK: vsli.16 d17, d16, #15 @ encoding: [0xdf,0xff,0x30,0x15]
72 vsli.16 d17, d16, #15
73 @ CHECK: vsli.32 d17, d16, #31 @ encoding: [0xff,0xff,0x30,0x15]
74 vsli.32 d17, d16, #31
75 @ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xff,0xff,0xb0,0x15]
76 vsli.64 d17, d16, #63
77 @ CHECK: vsli.8 q9, q8, #7 @ encoding: [0xcf,0xff,0x70,0x25]
78 vsli.8 q9, q8, #7
[all …]
Dneon-shiftaccum-encoding.s67 @ CHECK: vsli.8 d17, d16, #7 @ encoding: [0x30,0x15,0xcf,0xf3]
68 vsli.8 d17, d16, #7
69 @ CHECK: vsli.16 d17, d16, #15 @ encoding: [0x30,0x15,0xdf,0xf3]
70 vsli.16 d17, d16, #15
71 @ CHECK: vsli.32 d17, d16, #31 @ encoding: [0x30,0x15,0xff,0xf3]
72 vsli.32 d17, d16, #31
73 @ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xb0,0x15,0xff,0xf3]
74 vsli.64 d17, d16, #63
75 @ CHECK: vsli.8 q9, q8, #7 @ encoding: [0x70,0x25,0xcf,0xf3]
76 vsli.8 q9, q8, #7
[all …]
Dneon-shift-encoding.s116 @ CHECK: vsli.8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf3]
117 vsli.8 d16, d16, #7
118 @ CHECK: vsli.16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf3]
119 vsli.16 d16, d16, #15
120 @ CHECK: vsli.32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf3]
121 vsli.32 d16, d16, #31
122 @ CHECK: vsli.64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf3]
123 vsli.64 d16, d16, #63
124 @ CHECK: vsli.8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf3]
125 vsli.8 q8, q8, #7
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvshiftins.ll5 ;CHECK: vsli.8
14 ;CHECK: vsli.16
23 ;CHECK: vsli.32
32 ;CHECK: vsli.64
41 ;CHECK: vsli.8
50 ;CHECK: vsli.16
59 ;CHECK: vsli.32
68 ;CHECK: vsli.64
/external/llvm/test/CodeGen/ARM/
Dvshiftins.ll5 ;CHECK: vsli.8
14 ;CHECK: vsli.16
23 ;CHECK: vsli.32
32 ;CHECK: vsli.64
41 ;CHECK: vsli.8
50 ;CHECK: vsli.16
59 ;CHECK: vsli.32
68 ;CHECK: vsli.64
/external/boringssl/ios-arm/crypto/chacha/
Dchacha-armv4.S900 vsli.32 q1,q12,#12
902 vsli.32 q5,q13,#12
904 vsli.32 q9,q14,#12
924 vsli.32 q3,q12,#8
926 vsli.32 q7,q13,#8
928 vsli.32 q11,q14,#8
948 vsli.32 q1,q12,#7
950 vsli.32 q5,q13,#7
952 vsli.32 q9,q14,#7
1008 vsli.32 q1,q12,#12
[all …]
/external/boringssl/linux-arm/crypto/chacha/
Dchacha-armv4.S897 vsli.32 q1,q12,#12
899 vsli.32 q5,q13,#12
901 vsli.32 q9,q14,#12
921 vsli.32 q3,q12,#8
923 vsli.32 q7,q13,#8
925 vsli.32 q11,q14,#8
945 vsli.32 q1,q12,#7
947 vsli.32 q5,q13,#7
949 vsli.32 q9,q14,#7
1005 vsli.32 q1,q12,#12
[all …]
/external/arm-neon-tests/
Dref_vsli_n.c26 #define INSN_NAME vsli
Dref_vsXi_n.c35 #define INSN_NAME vsli
/external/boringssl/linux-arm/crypto/fipsmodule/
Dsha1-armv4-large.S741 vsli.32 q0,q12,#2
781 vsli.32 q1,q12,#2
818 vsli.32 q2,q12,#2
854 vsli.32 q3,q12,#2
891 vsli.32 q8,q12,#2
927 vsli.32 q9,q12,#2
963 vsli.32 q10,q12,#2
1008 vsli.32 q11,q12,#2
1053 vsli.32 q0,q12,#2
1097 vsli.32 q1,q12,#2
[all …]
/external/boringssl/ios-arm/crypto/fipsmodule/
Dsha1-armv4-large.S744 vsli.32 q0,q12,#2
784 vsli.32 q1,q12,#2
821 vsli.32 q2,q12,#2
857 vsli.32 q3,q12,#2
894 vsli.32 q8,q12,#2
930 vsli.32 q9,q12,#2
966 vsli.32 q10,q12,#2
1011 vsli.32 q11,q12,#2
1056 vsli.32 q0,q12,#2
1100 vsli.32 q1,q12,#2
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt1245 # CHECK: vsli.8 d16, d16, #7
1247 # CHECK: vsli.16 d16, d16, #15
1249 # CHECK: vsli.32 d16, d16, #31
1251 # CHECK: vsli.64 d16, d16, #63
1253 # CHECK: vsli.8 q8, q8, #7
1255 # CHECK: vsli.16 q8, q8, #15
1257 # CHECK: vsli.32 q8, q8, #31
1259 # CHECK: vsli.64 q8, q8, #63
1433 # CHECK: vsli.8 d17, d16, #7
1435 # CHECK: vsli.16 d17, d16, #15
[all …]
Dneont2.txt1242 # CHECK: vsli.8 d17, d16, #7
1244 # CHECK: vsli.16 d17, d16, #15
1246 # CHECK: vsli.32 d17, d16, #31
1248 # CHECK: vsli.64 d17, d16, #63
1250 # CHECK: vsli.8 q9, q8, #7
1252 # CHECK: vsli.16 q9, q8, #15
1254 # CHECK: vsli.32 q9, q8, #31
1256 # CHECK: vsli.64 q9, q8, #63
/external/llvm/test/MC/Disassembler/ARM/
Dneon.txt1245 # CHECK: vsli.8 d16, d16, #7
1247 # CHECK: vsli.16 d16, d16, #15
1249 # CHECK: vsli.32 d16, d16, #31
1251 # CHECK: vsli.64 d16, d16, #63
1253 # CHECK: vsli.8 q8, q8, #7
1255 # CHECK: vsli.16 q8, q8, #15
1257 # CHECK: vsli.32 q8, q8, #31
1259 # CHECK: vsli.64 q8, q8, #63
1433 # CHECK: vsli.8 d17, d16, #7
1435 # CHECK: vsli.16 d17, d16, #15
[all …]
Dneont2.txt1242 # CHECK: vsli.8 d17, d16, #7
1244 # CHECK: vsli.16 d17, d16, #15
1246 # CHECK: vsli.32 d17, d16, #31
1248 # CHECK: vsli.64 d17, d16, #63
1250 # CHECK: vsli.8 q9, q8, #7
1252 # CHECK: vsli.16 q9, q8, #15
1254 # CHECK: vsli.32 q9, q8, #31
1256 # CHECK: vsli.64 q9, q8, #63
/external/libavc/common/arm/
Dih264_deblk_chroma_a9.s293 vsli.16 q7, q7, #8 @
416 vsli.u16 d10, d10, #8
418 vsli.u32 q5, q5, #16
620 vsli.u16 d22, d22, #8
934 vsli.16 q7, q7, #8 @
1069 vsli.u16 d10, d10, #8
1074 vsli.u32 q5, q5, #16
1296 vsli.u16 d22, d22, #8
Dih264_deblk_luma_a9.s121 vsli.32 q7, q7, #8 @
127 vsli.32 q7, q7, #16 @Q7 = C0
/external/llvm/test/CodeGen/AArch64/
Darm64-vshift.ll1843 %tmp3 = call <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1)
1852 … %tmp3 = call <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1)
1861 … %tmp3 = call <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1)
1870 … %tmp3 = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1)
1879 … %tmp3 = call <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1)
1888 … %tmp3 = call <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1)
1897 … %tmp3 = call <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1)
1906 … %tmp3 = call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1)
1910 declare <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8>, <8 x i8>, i32) nounwind readnone
1911 declare <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16>, <4 x i16>, i32) nounwind readnone
[all …]
/external/libavc/encoder/arm/
Dime_distortion_metrics_a9q.s937 vsli.64 d10, d22, #32
938 vsli.64 d14, d18, #32
/external/vixl/src/aarch32/
Dassembler-aarch32.h5681 void vsli(Condition cond,
5686 void vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vsli() function
5687 vsli(al, dt, rd, rm, operand); in vsli()
5690 void vsli(Condition cond,
5695 void vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vsli() function
5696 vsli(al, dt, rd, rm, operand); in vsli()
Ddisasm-aarch32.h2347 void vsli(Condition cond,
2353 void vsli(Condition cond,
Dassembler-aarch32.cc24415 void Assembler::vsli(Condition cond, in vsli() function in vixl::aarch32::Assembler
24454 Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand); in vsli()
24457 void Assembler::vsli(Condition cond, in vsli() function in vixl::aarch32::Assembler
24496 Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand); in vsli()

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