/external/llvm/test/MC/ARM/ |
D | neon-shiftaccum-encoding.s | 3 vsra.s8 d17, d16, #8 4 vsra.s16 d15, d14, #16 5 vsra.s32 d13, d12, #32 6 vsra.s64 d11, d10, #64 7 vsra.s8 q7, q2, #8 8 vsra.s16 q3, q6, #16 9 vsra.s32 q9, q5, #32 10 vsra.s64 q8, q4, #64 11 vsra.u8 d17, d16, #8 12 vsra.u16 d11, d14, #11 [all …]
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D | neont2-shiftaccum-encoding.s | 5 vsra.s8 d17, d16, #8 6 vsra.s16 d15, d14, #16 7 vsra.s32 d13, d12, #32 8 vsra.s64 d11, d10, #64 9 vsra.s8 q7, q2, #8 10 vsra.s16 q3, q6, #16 11 vsra.s32 q9, q5, #32 12 vsra.s64 q8, q4, #64 13 vsra.u8 d17, d16, #8 14 vsra.u16 d11, d14, #11 [all …]
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D | neon-shift-encoding.s | 109 vsra.s8 d16, d6, #7 110 vsra.s16 d26, d18, #15 111 vsra.s32 d11, d10, #31 112 vsra.s64 d12, d19, #63 113 vsra.s8 q1, q8, #7 114 vsra.s16 q2, q7, #15 115 vsra.s32 q3, q6, #31 116 vsra.s64 q4, q5, #63 118 vsra.s8 d16, #7 119 vsra.s16 d15, #15 [all …]
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | neont2-shiftaccum-encoding.s | 5 @ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0xc8,0xef,0x30,0x11] 6 vsra.s8 d17, d16, #8 7 @ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0xd0,0xef,0x30,0x11] 8 vsra.s16 d17, d16, #16 9 @ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0xe0,0xef,0x30,0x11] 10 vsra.s32 d17, d16, #32 11 @ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x11] 12 vsra.s64 d17, d16, #64 13 @ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0xc8,0xef,0x72,0x01] 14 vsra.s8 q8, q9, #8 [all …]
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D | neon-shiftaccum-encoding.s | 3 @ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf2] 4 vsra.s8 d17, d16, #8 5 @ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xf2] 6 vsra.s16 d17, d16, #16 7 @ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xf2] 8 vsra.s32 d17, d16, #32 9 @ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xf2] 10 vsra.s64 d17, d16, #64 11 @ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xf2] 12 vsra.s8 q8, q9, #8 [all …]
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D | neon-shift-encoding.s | 68 @ CHECK: vsra.u8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf3] 69 vsra.u8 d16, d16, #7 70 @ CHECK: vsra.u16 d16, d16, #15 @ encoding: [0x30,0x01,0xd1,0xf3] 71 vsra.u16 d16, d16, #15 72 @ CHECK: vsra.u32 d16, d16, #31 @ encoding: [0x30,0x01,0xe1,0xf3] 73 vsra.u32 d16, d16, #31 74 @ CHECK: vsra.u64 d16, d16, #63 @ encoding: [0xb0,0x01,0xc1,0xf3] 75 vsra.u64 d16, d16, #63 76 @ CHECK: vsra.u8 q8, q8, #7 @ encoding: [0x70,0x01,0xc9,0xf3] 77 vsra.u8 q8, q8, #7 [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | vsra.ll | 5 ;CHECK: vsra.s8 15 ;CHECK: vsra.s16 25 ;CHECK: vsra.s32 35 ;CHECK: vsra.s64 45 ;CHECK: vsra.s8 55 ;CHECK: vsra.s16 65 ;CHECK: vsra.s32 75 ;CHECK: vsra.s64 85 ;CHECK: vsra.u8 95 ;CHECK: vsra.u16 [all …]
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/external/llvm/test/CodeGen/ARM/ |
D | vsra.ll | 5 ;CHECK: vsra.s8 15 ;CHECK: vsra.s16 25 ;CHECK: vsra.s32 35 ;CHECK: vsra.s64 45 ;CHECK: vsra.s8 55 ;CHECK: vsra.s16 65 ;CHECK: vsra.s32 75 ;CHECK: vsra.s64 85 ;CHECK: vsra.u8 95 ;CHECK: vsra.u16 [all …]
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | neon.txt | 1197 # CHECK: vsra.u8 d16, d16, #7 1199 # CHECK: vsra.u16 d16, d16, #15 1201 # CHECK: vsra.u32 d16, d16, #31 1203 # CHECK: vsra.u64 d16, d16, #63 1205 # CHECK: vsra.u8 q8, q8, #7 1207 # CHECK: vsra.u16 q8, q8, #15 1209 # CHECK: vsra.u32 q8, q8, #31 1211 # CHECK: vsra.u64 q8, q8, #63 1213 # CHECK: vsra.s8 d16, d16, #7 1215 # CHECK: vsra.s16 d16, d16, #15 [all …]
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D | neont2.txt | 1178 # CHECK: vsra.s8 d17, d16, #8 1180 # CHECK: vsra.s16 d17, d16, #16 1182 # CHECK: vsra.s32 d17, d16, #32 1184 # CHECK: vsra.s64 d17, d16, #64 1186 # CHECK: vsra.s8 q8, q9, #8 1188 # CHECK: vsra.s16 q8, q9, #16 1190 # CHECK: vsra.s32 q8, q9, #32 1192 # CHECK: vsra.s64 q8, q9, #64 1194 # CHECK: vsra.u8 d17, d16, #8 1196 # CHECK: vsra.u16 d17, d16, #16 [all …]
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/external/llvm/test/MC/Disassembler/ARM/ |
D | neon.txt | 1197 # CHECK: vsra.u8 d16, d16, #7 1199 # CHECK: vsra.u16 d16, d16, #15 1201 # CHECK: vsra.u32 d16, d16, #31 1203 # CHECK: vsra.u64 d16, d16, #63 1205 # CHECK: vsra.u8 q8, q8, #7 1207 # CHECK: vsra.u16 q8, q8, #15 1209 # CHECK: vsra.u32 q8, q8, #31 1211 # CHECK: vsra.u64 q8, q8, #63 1213 # CHECK: vsra.s8 d16, d16, #7 1215 # CHECK: vsra.s16 d16, d16, #15 [all …]
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D | neont2.txt | 1178 # CHECK: vsra.s8 d17, d16, #8 1180 # CHECK: vsra.s16 d17, d16, #16 1182 # CHECK: vsra.s32 d17, d16, #32 1184 # CHECK: vsra.s64 d17, d16, #64 1186 # CHECK: vsra.s8 q8, q9, #8 1188 # CHECK: vsra.s16 q8, q9, #16 1190 # CHECK: vsra.s32 q8, q9, #32 1192 # CHECK: vsra.s64 q8, q9, #64 1194 # CHECK: vsra.u8 d17, d16, #8 1196 # CHECK: vsra.u16 d17, d16, #16 [all …]
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/external/arm-neon-tests/ |
D | ref_vsra_n.c | 40 vsra##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \ in exec_vsra_n()
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/external/libavc/common/arm/ |
D | ih264_iquant_itrans_recon_a9.s | 616 vsra.s16 q2, q6, #0x1 @ Q2 = y6 658 vsra.s16 q6, q9, #0x2 @ Q6 = z3 689 vsra.s16 q9, q7, #0x2 @ Q9 = z1 735 vsra.s16 q2, q6, #0x1 @ Q2 = y6 780 vsra.s16 q6, q9, #0x2 @ Q6 = z3 810 vsra.s16 q9, q7, #0x2 @ Q9 = z1
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D | ih264_deblk_luma_a9.s | 254 vsra.u8 q10, q0, #2 @((Alpha >> 2) + 2) 869 vsra.u8 d14, d15, #2 @alpha >>2 +2
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/external/llvm/include/llvm/IR/ |
D | IntrinsicsSystemZ.td | 308 def int_s390_vsra : SystemZBinary<"vsra", llvm_v16i8_ty>;
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/external/llvm/test/MC/SystemZ/ |
D | insn-good-z13.s | 4133 #CHECK: vsra %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7e] 4134 #CHECK: vsra %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7e] 4135 #CHECK: vsra %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7e] 4136 #CHECK: vsra %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7e] 4137 #CHECK: vsra %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7e] 4139 vsra %v0, %v0, %v0 4140 vsra %v0, %v0, %v31 4141 vsra %v0, %v31, %v0 4142 vsra %v31, %v0, %v0 4143 vsra %v18, %v3, %v20
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D | insn-bad-zEC12.s | 1304 #CHECK: vsra %v0, %v0, %v0 1306 vsra %v0, %v0, %v0
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 5705 void vsra(Condition cond, 5710 void vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vsra() function 5711 vsra(al, dt, rd, rm, operand); in vsra() 5714 void vsra(Condition cond, 5719 void vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vsra() function 5720 vsra(al, dt, rd, rm, operand); in vsra()
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D | disasm-aarch32.h | 2363 void vsra(Condition cond, 2369 void vsra(Condition cond,
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/external/llvm/test/MC/Disassembler/SystemZ/ |
D | insns-z13.txt | 2741 #CHECK: vsra %v0, %v0, %v0 2744 #CHECK: vsra %v18, %v3, %v20 2747 #CHECK: vsra %v31, %v31, %v31
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/external/v8/src/s390/ |
D | constants-s390.h | 573 V(vsra, VSRA, 0xE77E) /* type = VRR_C VECTOR SHIFT RIGHT ARITHMETIC */ \
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/external/llvm/test/CodeGen/SystemZ/ |
D | vec-intrinsics.ll | 110 declare <16 x i8> @llvm.s390.vsra(<16 x i8>, <16 x i8>) 1513 ; CHECK: vsra %v24, %v24, %v26 1515 %res = call <16 x i8> @llvm.s390.vsra(<16 x i8> %a, <16 x i8> %b)
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZInstrVector.td | 599 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrNEON.td | 4207 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>; 4208 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
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