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Searched refs:vsri (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/test/MC/ARM/
Dneon-shiftaccum-encoding.s150 vsri.8 d28, d11, #8
151 vsri.16 d26, d12, #16
152 vsri.32 d24, d13, #32
153 vsri.64 d21, d14, #64
154 vsri.8 q1, q8, #8
155 vsri.16 q5, q2, #16
156 vsri.32 q7, q4, #32
157 vsri.64 q9, q6, #64
168 vsri.8 d11, #8
169 vsri.16 d12, #16
[all …]
Dneont2-shiftaccum-encoding.s153 vsri.8 d28, d11, #8
154 vsri.16 d26, d12, #16
155 vsri.32 d24, d13, #32
156 vsri.64 d21, d14, #64
157 vsri.8 q1, q8, #8
158 vsri.16 q5, q2, #16
159 vsri.32 q7, q4, #32
160 vsri.64 q9, q6, #64
171 vsri.8 d11, #8
172 vsri.16 d12, #16
[all …]
Dneon-shift-encoding.s181 vsri.8 d16, d6, #7
182 vsri.16 d26, d18, #15
183 vsri.32 d11, d10, #31
184 vsri.64 d12, d19, #63
185 vsri.8 q1, q8, #7
186 vsri.16 q2, q7, #15
187 vsri.32 q3, q6, #31
188 vsri.64 q4, q5, #63
190 vsri.8 d16, #7
191 vsri.16 d15, #15
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-shiftaccum-encoding.s85 @ CHECK: vsri.8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x14]
86 vsri.8 d17, d16, #8
87 @ CHECK: vsri.16 d17, d16, #16 @ encoding: [0xd0,0xff,0x30,0x14]
88 vsri.16 d17, d16, #16
89 @ CHECK: vsri.32 d17, d16, #32 @ encoding: [0xe0,0xff,0x30,0x14]
90 vsri.32 d17, d16, #32
91 @ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x14]
92 vsri.64 d17, d16, #64
93 @ CHECK: vsri.8 q9, q8, #8 @ encoding: [0xc8,0xff,0x70,0x24]
94 vsri.8 q9, q8, #8
[all …]
Dneon-shiftaccum-encoding.s83 @ CHECK: vsri.8 d17, d16, #8 @ encoding: [0x30,0x14,0xc8,0xf3]
84 vsri.8 d17, d16, #8
85 @ CHECK: vsri.16 d17, d16, #16 @ encoding: [0x30,0x14,0xd0,0xf3]
86 vsri.16 d17, d16, #16
87 @ CHECK: vsri.32 d17, d16, #32 @ encoding: [0x30,0x14,0xe0,0xf3]
88 vsri.32 d17, d16, #32
89 @ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xb0,0x14,0xc0,0xf3]
90 vsri.64 d17, d16, #64
91 @ CHECK: vsri.8 q9, q8, #8 @ encoding: [0x70,0x24,0xc8,0xf3]
92 vsri.8 q9, q8, #8
[all …]
Dneon-shift-encoding.s100 @ CHECK: vsri.8 d16, d16, #7 @ encoding: [0x30,0x04,0xc9,0xf3]
101 vsri.8 d16, d16, #7
102 @ CHECK: vsri.16 d16, d16, #15 @ encoding: [0x30,0x04,0xd1,0xf3]
103 vsri.16 d16, d16, #15
104 @ CHECK: vsri.32 d16, d16, #31 @ encoding: [0x30,0x04,0xe1,0xf3]
105 vsri.32 d16, d16, #31
106 @ CHECK: vsri.64 d16, d16, #63 @ encoding: [0xb0,0x04,0xc1,0xf3]
107 vsri.64 d16, d16, #63
108 @ CHECK: vsri.8 q8, q8, #7 @ encoding: [0x70,0x04,0xc9,0xf3]
109 vsri.8 q8, q8, #7
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvshiftins.ll77 ;CHECK: vsri.8
86 ;CHECK: vsri.16
95 ;CHECK: vsri.32
104 ;CHECK: vsri.64
113 ;CHECK: vsri.8
122 ;CHECK: vsri.16
131 ;CHECK: vsri.32
140 ;CHECK: vsri.64
/external/llvm/test/CodeGen/ARM/
Dvshiftins.ll77 ;CHECK: vsri.8
86 ;CHECK: vsri.16
95 ;CHECK: vsri.32
104 ;CHECK: vsri.64
113 ;CHECK: vsri.8
122 ;CHECK: vsri.16
131 ;CHECK: vsri.32
140 ;CHECK: vsri.64
/external/arm-neon-tests/
Dref_vsri_n.c26 #define INSN_NAME vsri
/external/regex-re2/
DCONTRIBUTORS35 Srinivasan Venkatachary <vsri@google.com>
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon-tests.txt54 # CHECK: vsri.32 q15, q0, #1
Dneon.txt1229 # CHECK: vsri.8 d16, d16, #7
1231 # CHECK: vsri.16 d16, d16, #15
1233 # CHECK: vsri.32 d16, d16, #31
1235 # CHECK: vsri.64 d16, d16, #63
1237 # CHECK: vsri.8 q8, q8, #7
1239 # CHECK: vsri.16 q8, q8, #15
1241 # CHECK: vsri.32 q8, q8, #31
1243 # CHECK: vsri.64 q8, q8, #63
1449 # CHECK: vsri.8 d17, d16, #8
1451 # CHECK: vsri.16 d17, d16, #16
[all …]
Dneont2.txt1258 # CHECK: vsri.8 d17, d16, #8
1260 # CHECK: vsri.16 d17, d16, #16
1262 # CHECK: vsri.32 d17, d16, #32
1264 # CHECK: vsri.64 d17, d16, #64
1266 # CHECK: vsri.8 q9, q8, #8
1268 # CHECK: vsri.16 q9, q8, #16
1270 # CHECK: vsri.32 q9, q8, #32
1272 # CHECK: vsri.64 q9, q8, #64
/external/llvm/test/MC/Disassembler/ARM/
Dneon-tests.txt54 # CHECK: vsri.32 q15, q0, #1
Dneon.txt1229 # CHECK: vsri.8 d16, d16, #7
1231 # CHECK: vsri.16 d16, d16, #15
1233 # CHECK: vsri.32 d16, d16, #31
1235 # CHECK: vsri.64 d16, d16, #63
1237 # CHECK: vsri.8 q8, q8, #7
1239 # CHECK: vsri.16 q8, q8, #15
1241 # CHECK: vsri.32 q8, q8, #31
1243 # CHECK: vsri.64 q8, q8, #63
1449 # CHECK: vsri.8 d17, d16, #8
1451 # CHECK: vsri.16 d17, d16, #16
[all …]
Dneont2.txt1258 # CHECK: vsri.8 d17, d16, #8
1260 # CHECK: vsri.16 d17, d16, #16
1262 # CHECK: vsri.32 d17, d16, #32
1264 # CHECK: vsri.64 d17, d16, #64
1266 # CHECK: vsri.8 q9, q8, #8
1268 # CHECK: vsri.16 q9, q8, #16
1270 # CHECK: vsri.32 q9, q8, #32
1272 # CHECK: vsri.64 q9, q8, #64
/external/boringssl/linux-arm/crypto/fipsmodule/
Dsha1-armv4-large.S562 vsri.32 q8,q12,#31
609 vsri.32 q9,q12,#31
655 vsri.32 q10,q12,#31
701 vsri.32 q11,q12,#31
/external/boringssl/ios-arm/crypto/fipsmodule/
Dsha1-armv4-large.S565 vsri.32 q8,q12,#31
612 vsri.32 q9,q12,#31
658 vsri.32 q10,q12,#31
704 vsri.32 q11,q12,#31
/external/libjpeg-turbo/simd/
Djsimd_arm_neon.S1409 vsri.u16 q15, q13, #5
1410 vsri.u16 q15, q14, #11
1455 vsri.u16 q15, q13, #5
1457 vsri.u16 q15, q14, #11
/external/vixl/src/aarch32/
Dassembler-aarch32.h5723 void vsri(Condition cond,
5728 void vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vsri() function
5729 vsri(al, dt, rd, rm, operand); in vsri()
5732 void vsri(Condition cond,
5737 void vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vsri() function
5738 vsri(al, dt, rd, rm, operand); in vsri()
Ddisasm-aarch32.h2375 void vsri(Condition cond,
2381 void vsri(Condition cond,
Dassembler-aarch32.cc24625 void Assembler::vsri(Condition cond, in vsri() function in vixl::aarch32::Assembler
24664 Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand); in vsri()
24667 void Assembler::vsri(Condition cond, in vsri() function in vixl::aarch32::Assembler
24706 Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand); in vsri()
Ddisasm-aarch32.cc6703 void Disassembler::vsri(Condition cond, in vsri() function in vixl::aarch32::Disassembler
6717 void Disassembler::vsri(Condition cond, in vsri() function in vixl::aarch32::Disassembler
31787 vsri(CurrentCond(), in DecodeT32()
36969 vsri(CurrentCond(), in DecodeT32()
44377 vsri(al, dt, DRegister(rd), DRegister(rm), imm); in DecodeA32()
48539 vsri(al, dt, QRegister(rd), QRegister(rm), imm); in DecodeA32()
Dmacro-assembler-aarch32.h9986 vsri(cond, dt, rd, rm, operand); in Vsri()
10004 vsri(cond, dt, rd, rm, operand); in Vsri()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td4217 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;

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