Home
last modified time | relevance | path

Searched refs:wreg (Results 1 – 6 of 6) sorted by relevance

/external/v8/src/arm64/
Dsimulator-arm64.cc717 TraceSim("Arguments: %f, %d\n", dreg(0), wreg(0)); in DoRuntimeCall()
718 double result = target(dreg(0), wreg(0)); in DoRuntimeCall()
1406 case CBZ_w: take_branch = (wreg(rt) == 0); break; in VisitCompareBranch()
1408 case CBNZ_w: take_branch = (wreg(rt) != 0); break; in VisitCompareBranch()
1458 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1481 uint32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift); in VisitAddSubExtended()
1505 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1554 ConditionalCompareHelper(instr, static_cast<uint32_t>(wreg(instr->Rm()))); in VisitConditionalCompareRegister()
1662 case STRB_w: MemoryWrite<uint8_t>(address, wreg(srcdst)); break; in LoadStoreHelper()
1663 case STRH_w: MemoryWrite<uint16_t>(address, wreg(srcdst)); break; in LoadStoreHelper()
[all …]
Dsimulator-arm64.h344 int32_t wreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
/external/vixl/test/aarch64/examples/
Dtest-examples.cc506 VIXL_CHECK(regs.wreg(0) == y); in TEST()
507 VIXL_CHECK(regs.wreg(1) == x); in TEST()
602 VIXL_CHECK(regs.wreg<int32_t>(0) == RUNTIME_CALLS_EXPECTED(A, B)); \
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h81 inline int32_t wreg(unsigned code) const { in wreg() function
Dtest-utils-aarch64.cc145 uint32_t result_w = core->wreg(reg.GetCode()); in Equal32()
/external/vixl/src/aarch64/
Dsimulator-aarch64.h880 int32_t wreg(unsigned code,