Searched refs:write_enable (Results 1 – 13 of 13) sorted by relevance
| /external/mesa3d/src/gallium/drivers/ilo/ |
| D | ilo_blitter_rectlist.c | 390 info.depth.write_enable = true; in ilo_blitter_rectlist_clear_zs()
462 info.depth.write_enable = true; in ilo_blitter_rectlist_resolve_z()
498 info.depth.write_enable = true; in ilo_blitter_rectlist_resolve_hiz()
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| D | ilo_state.c | 1226 dsa->depth.write_enable = state->depth.writemask; in ilo_create_depth_stencil_alpha_state()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_buffer_objects.c | 50 drm_intel_bo *bo, int write_enable, in brw_bo_map() argument
54 return drm_intel_bo_map(bo, write_enable); in brw_bo_map()
58 int ret = drm_intel_bo_map(bo, write_enable); in brw_bo_map()
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| D | brw_context.h | 1444 int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
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| /external/libdrm/intel/ |
| D | intel_bufmgr.c | 105 drm_intel_bo_map(drm_intel_bo *buf, int write_enable) in drm_intel_bo_map() argument
107 return buf->bufmgr->bo_map(buf, write_enable); in drm_intel_bo_map()
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| D | intel_bufmgr.h | 133 int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
198 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
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| D | intel_bufmgr_priv.h | 114 int (*bo_map) (drm_intel_bo *bo, int write_enable);
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| D | intel_bufmgr_fake.c | 999 drm_intel_fake_bo_map_locked(drm_intel_bo *bo, int write_enable) in drm_intel_fake_bo_map_locked() argument
1047 if (write_enable) in drm_intel_fake_bo_map_locked()
1072 drm_intel_fake_bo_map(drm_intel_bo *bo, int write_enable) in drm_intel_fake_bo_map() argument
1079 ret = drm_intel_fake_bo_map_locked(bo, write_enable); in drm_intel_fake_bo_map()
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| D | intel_bufmgr_gem.c | 1456 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) in drm_intel_gem_bo_map() argument
1506 if (write_enable) in drm_intel_gem_bo_map()
1519 if (write_enable) in drm_intel_gem_bo_map()
1902 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable) in drm_intel_gem_bo_start_gtt_access() argument
1912 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0; in drm_intel_gem_bo_start_gtt_access()
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| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| D | ilo_state_cc.h | 95 bool write_enable; member
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| D | intel_winsys.h | 244 intel_bo_map(struct intel_bo *bo, bool write_enable);
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| D | ilo_state_cc.c | 76 if (depth->test_enable || depth->write_enable) in cc_validate_gen6_depth()
155 if (depth->write_enable) in cc_set_gen6_DEPTH_STENCIL_STATE()
228 if (depth->write_enable) in cc_set_gen8_3DSTATE_WM_DEPTH_STENCIL()
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| /external/mesa3d/src/gallium/winsys/intel/drm/ |
| D | intel_drm_winsys.c | 519 intel_bo_map(struct intel_bo *bo, bool write_enable) in intel_bo_map() argument
523 err = drm_intel_bo_map(gem_bo(bo), write_enable); in intel_bo_map()
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