Searched refs:wsbh (Results 1 – 25 of 47) sorted by relevance
12
| /external/valgrind/none/tests/mips64/ |
| D | rotate_swap.stdout.exp-mips64r2 | 107 wsbh :: in 0x2000ffffffffffff, out 0xffffffffffffffff
108 wsbh :: in 0xffff0000ffffffff, out 0xffffffffffffffff
109 wsbh :: in 0x2000ffffffffffff, out 0xffffffffffffffff
110 wsbh :: in 0x2000ffffeeeeffff, out 0xffffffffeeeeffff
111 wsbh :: in 0x2000ffffffffffff, out 0xffffffffffffffff
112 wsbh :: in 0x31415927ffffffff, out 0xffffffffffffffff
113 wsbh :: in 0x2000ffffffffffff, out 0xffffffffffffffff
114 wsbh :: in 0x2000ffffffccccff, out 0xffffffffccffffcc
115 wsbh :: in 0xeeeeffffffffffff, out 0xffffffffffffffff
116 wsbh :: in 0x2000ffff0000ffff, out 0xffff
[all …]
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| /external/llvm/test/CodeGen/Mips/ |
| D | bswap.ll | 8 ; MIPS32: wsbh $[[R0:[0-9]+]]
12 ; MIPS64: wsbh $[[R0:[0-9]+]]
35 ; MIPS32: wsbh $[[R0:[0-9]+]]
37 ; MIPS32: wsbh $[[R0:[0-9]+]]
75 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
77 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
79 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
81 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
85 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
87 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
[all …]
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| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | bswap1.ll | 27 ; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]]
51 ; 32R2: wsbh $[[TMP:[0-9]+]], $[[B_VAL]]
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| /external/llvm/test/MC/Mips/ |
| D | mips-alu-instructions.s | 36 # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
67 wsbh $6, $7
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| D | mips64-alu-instructions.s | 33 # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
61 wsbh $6, $7
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| /external/llvm/test/MC/Mips/mips64/ |
| D | invalid-mips64r2.s | 31 …wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | invalid-mips64r2.s | 33 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | invalid-mips64r2.s | 39 …wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Mips/mips32/ |
| D | invalid-mips32r2.s | 36 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips32r2.s | 68 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | valid.s | 141 wsbh $3, $4 # CHECK: wsbh $3, $4 # encoding: [0x00,0x64,0x7b,0x3c]
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| D | invalid.s | 101 wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
102 wsbh $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | invalid.s | 75 wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
76 wsbh $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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| D | valid.s | 123 wsbh $3, $4 # CHECK: wsbh $3, $4 # encoding: [0x00,0x64,0x7b,0x3c]
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| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid.txt | 121 0x01 0x26 0x7b 0x3c # CHECK: wsbh $9, $6
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| D | valid-el.txt | 121 0x26 0x01 0x3c 0x7b # CHECK: wsbh $9, $6
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| /external/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 244 wsbh $k1,$9
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| /external/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 245 wsbh $k1,$9
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| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 244 wsbh $k1,$9
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| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-mips32r3-el.txt | 169 0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
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| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-mips32r2-el.txt | 173 0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
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| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-mips32r5-el.txt | 169 0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
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| /external/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 140 // ehb, rdhwr, rdpgpr, wrpgpr, wsbh
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| /external/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 321 wsbh $k1,$9
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| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 321 wsbh $k1,$9
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